Processor Memory Mapping Translation Unit

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Solution Overview

Problem

Existing parallel processing systems face challenges in efficiently mapping requests from a central processing unit using memory-mapped input-output space to a second processing domain, limiting their ability to perform concurrent operations effectively.

Innovation Solution

A processor is designed to convert requests addressed to the input-output space of a central processing unit into corresponding commands that simulate operations within a second processing domain, allowing for simultaneous execution and access to information across multiple micro-engines, thereby enabling efficient parallel processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a central processing unit uses memory-mapped input-output space to access components, then the CPU can efficiently access and control hardware resources, but the ability to map these requests to a second processing domain becomes complex and limited

Engineering Contradiction:

ImproveCPU access to hardware resourcesVSAvoidrequest mapping to second processing domain

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

A translation unit is introduced as an intermediary component between the CPU and the second processing domain. This translation unit receives requests from the CPU addressed to memory-mapped input-output space and converts them into corresponding commands that simulate operations within the second processing domain, thereby resolving the mapping complexity while preserving CPU access efficiency

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a virtual copy of the input-output space mapping in the second processing domain. By simulating the same memory-mapped interface structure in the second domain, the system allows requests to be mapped without complex translation, as the second domain replicates the expected address space layout

Inventive Principle:

Principle #26Copying

2Productivity

If parallel processing executes multiple functions concurrently, then processing efficiency improves, but the ability to maintain independent thread execution and reduce latency becomes challenging

Engineering Contradiction:

Improveconcurrent execution efficiencyVSAvoidthread execution latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The processing system is segmented into multiple independent processing domains, each capable of executing threads independently. The translation unit segments the request mapping function, allowing each processing domain to operate autonomously without blocking other threads, thereby reducing latency while maintaining concurrent execution efficiency

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system implements dynamic request routing where requests are translated and dispatched to appropriate processing domains based on current system state. This dynamic approach allows threads to be routed to available domains for execution, minimizing waiting time and reducing latency while preserving parallel processing efficiency

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8738886B2Memory mapping in a processor having multiple programmable units

Publication Date: 2014.05.27 INTEL CORP

AI summary

A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.