Processor–Memory Data Processing With a High-Speed Parallel Bus
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Solution Overview
Problem
The speed at which storage bandwidth increases cannot keep pace with the performance improvement of processors, leading to inefficiencies in data access and transmission between memory and processor.
Innovation Solution
A data processing system utilizing a high-speed parallel bus connecting a computing subsystem and a memory subsystem, with bus interfaces capable of higher-order modulation and specific pin arrangements to enhance data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional storage bandwidth is used, then device complexity is reduced, but data transmission speed cannot keep pace with processor performance improvement
Solution Approach 1:
The bus interface is divided into separate transmitting and receiving units, with each unit independently handling modulation or demodulation operations. This segmentation allows the system to achieve higher-order modulation capabilities while maintaining clear functional separation, thereby improving data transmission speed without excessively increasing overall system complexity.
Solution Approach 2:
The system employs higher-order modulation schemes that can dynamically adapt to different data transmission requirements. The bus interface supports flexible modulation orders, allowing the data transmission speed to be dynamically adjusted to match processor performance improvements while managing complexity through standardized interface designs.
2Productivity
If higher-order modulation is implemented, then data transmission efficiency is improved, but signal transmission complexity increases
Solution Approach 1:
The modulation functionality is segmented into dedicated transmitting and receiving units. The transmitting unit handles higher-order modulation independently, while the receiving unit handles demodulation independently. This segmentation concentrates complexity in specialized modules rather than distributing it throughout the entire system, thereby improving data transmission efficiency while managing signal transmission complexity through modular design.
3Speed
If storage bandwidth is increased, then data access speed improves, but it still cannot match processor performance improvement
Solution Approach 1:
The system changes the modulation order parameter to achieve higher data transmission rates within the same physical bandwidth resources. By implementing higher-order modulation schemes, the effective data access speed is improved without requiring proportional increases in bandwidth resources, allowing storage subsystem performance to better match processor performance improvements.
Data Source
AI summary
A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.