Processor-Memory Interface Using Parity to Eliminate Stored ECC Bits
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Solution Overview
Problem
Conventional sub-micron system-on-a-chip (SoC) designs face data integrity issues due to noise-injection events like alpha particle strikes, which corrupt memory contents, and existing error correction schemes like ECC require additional storage and complexity, limiting the ability to implement multiple memory configurations on the same processor-memory interface port.
Innovation Solution
An interface device that uses a parity encoder, ECC encoder, and parity decoder to provide ECC-based protection for processing devices and parity-based protection for memory devices, eliminating the need for storing ECC bits in memory and allowing mixed memory types on the same interface port, with the processor calculating ECC bits on the fly and using pre-existing ECC/parity read logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC bits are stored in memory, then data integrity is improved, but memory area and system complexity increase
Solution Approach 1:
The patent extracts the ECC bit storage function from the memory device and relocates it to the processor. The processor calculates and stores ECC bits in its own storage, while the memory device only stores data bits. This separation eliminates the need for additional memory area dedicated to ECC bits while maintaining data integrity protection.
Solution Approach 2:
The patent introduces an interface device as an intermediary between the processor and memory device. This interface device coordinates the ECC bit generation, storage, and verification processes, enabling the processor to provide ECC protection without the memory device needing to store ECC bits directly.
2Reliability
If ECC protection is implemented, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent enables the processor to self-serve by calculating and managing its own ECC bits internally. The processor uses its existing computational resources to generate ECC bits when writing data and to verify them when reading data, eliminating the need for separate dedicated ECC hardware circuits in the memory system.
Solution Approach 2:
The patent makes the processor multi-functional by having it perform both data processing and ECC bit generation/verification functions. The processor's existing ALU and storage resources are utilized for ECC operations, eliminating the need for separate dedicated ECC hardware and reducing overall system complexity.
3Adaptability or versatility
If the same interface port supports multiple memory configurations, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent introduces dynamic configuration capability to the interface device, allowing it to adaptively switch between different memory modes (ECC-protected and non-ECC) based on the connected memory device type. The interface can dynamically adjust its operation to match the capabilities of the attached memory, enabling support for multiple memory configurations without requiring separate dedicated interfaces for each type.
Data Source
AI summary
An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.