Processor Memory Mapped Peripheral for Hazard-Free Data Flow
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Solution Overview
Problem
Existing shared memory communication systems face challenges in controlling data flow between processors, particularly in preventing read after write (RAW) and write after read (WAR) hazards, and require large pointers for efficient communication, which can be problematic across separate chips with high routing distance and different clock domains.
Innovation Solution
A processor module with a memory mapped peripheral that uses a data request generator and acknowledgement waiting signal generator to manage data flow through a shared memory system, minimizing the number of connecting signals and being tolerant of high propagation latency, utilizing flip-flops and logic combinators to synchronize signals across clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large pointers (32 bits or more) are used to address the whole buffer, then the receiver can accurately track data locations, but the communication overhead between processors increases significantly
Solution Approach 1:
The patent segments the pointer addressing space by using separate shared memory locations to store different segments of the pointer values (e.g., high-order bits and low-order bits separately). This allows the system to maintain full addressing capability while reducing the number of bits that need to be transmitted over the communication interface between processors.
Solution Approach 2:
The patent moves the pointer storage from the communication domain to the memory domain by utilizing shared memory locations to store pointer values. This dimensional shift allows the system to maintain large pointer values without increasing communication overhead, as the pointers reside in memory rather than being transmitted through communication channels.
2Device complexity
If additional shared memory locations are used to store read and write pointer values, then pointer communication between processors is eliminated, but communication loads increase as processors must poll the pointer locations
Solution Approach 1:
The patent implements a polling mechanism where processors autonomously check the shared memory locations for updated pointer values. This self-service approach eliminates the need for complex inter-processor communication infrastructure while maintaining communication efficiency through automated, event-driven polling rather than continuous active monitoring.
Solution Approach 2:
The system uses feedback through the polling mechanism where processors periodically check the shared memory for pointer updates. This feedback loop ensures that processors are notified of data availability without requiring direct communication channels, as the presence of updated pointer values in shared memory serves as the feedback signal.
3Reliability
If read and write pointers are communicated between processors separated by significant routing distance, then flow control can be implemented, but the overhead of communicating multiple wires becomes unacceptably high
Solution Approach 1:
The patent introduces shared memory as an intermediary between processors for storing pointer values. Instead of directly communicating pointer values through multiple wire channels between distant processors, the shared memory acts as a mediator that holds the pointer information, reducing the communication infrastructure requirements while maintaining flow control capability.
4Adaptability or versatility
If processors operate in separate clock domains, then each processor can operate independently, but additional hardware is required to ensure pointers are communicated safely without corruption
Solution Approach 1:
The patent uses periodic polling of shared memory locations by processors to retrieve pointer values. This periodic action naturally handles clock domain independence by allowing each processor to read pointer values at its own clock rate from the shared memory, eliminating the need for complex synchronization hardware while ensuring data integrity through the memory's inherent synchronization capabilities.
Data Source
AI summary
A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.