Processor Memory Segment Registers for Kernel User Space Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The MIPS processor architecture limits kernel mode memory access to 512 MB due to fixed memory address segments, hindering the expansion of accessible physical memory and complicating virtualization and system memory management.
Innovation Solution
Implementing memory segment configuration registers to allow programmable memory address segments with customizable access modes, cache features, and mapping attributes, enabling kernel mode access to user space virtual addresses and enhancing memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fixed memory address segments are used in MIPS processor architecture, then memory management is simplified and system stability is maintained, but kernel mode memory access is limited to 512 MB and physical memory expansion is hindered
Solution Approach 1:
The patent transforms the static, fixed memory address segment configuration into a dynamic, programmable system. Configuration registers allow the kernel to programmatically define memory segments, their attributes (cached/unmapped, access permissions), and mappings at runtime. This enables the system to adapt memory segmentation to different operational needs while maintaining stability through controlled modification of segment parameters.
Solution Approach 2:
The invention changes the parameters of memory address segments from fixed to configurable. By introducing configuration registers that store segment base addresses, limits, and attributes, the system can modify segment parameters (size, position, access mode, cacheability) without changing the fundamental architecture. This allows expansion beyond 512 MB while maintaining the segmented memory management model.
2Productivity
If kernel mode is restricted to specific memory segments (kseg0, kseg1, kseg2, kseg3), then memory protection and isolation are maintained, but direct access to user space virtual addresses is prevented and system performance deteriorates
Solution Approach 1:
The patent introduces configuration registers as intermediaries between the kernel and user space memory segments. These registers act as controlled access points that allow the kernel to define and access user space virtual addresses through programmable segment mappings. This intermediary mechanism maintains the protective segmentation model while enabling efficient kernel access when needed, avoiding the performance penalty of mode switching.
3Quantity of substance
If HighMem enhancement is used to access memory beyond kseg0, then physical memory accessibility is extended, but temporary mappings must be created on the fly which incurs performance penalties
Solution Approach 1:
The patent applies preliminary action by pre-configuring memory segment parameters and attributes in configuration registers before access is needed. Instead of creating temporary mappings on the fly (as in HighMem), the system establishes segment definitions, base addresses, and access attributes in advance through programmable configuration. This preliminary setup eliminates runtime mapping creation overhead and enables direct, efficient access to extended physical memory.
Data Source
AI summary
A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.