Processor Memory Segmentation for Display Correction Data
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Solution Overview
Problem
Current display devices for mobile terminals face challenges in performing image correction processing due to the limitations of chip size and cost associated with large-capacity RAM, particularly for high-resolution OLED displays, which require significant compensation data.
Innovation Solution
A processor with internal volatile memory divided into parts for storing correction data, image signal data, and application data, and an external display driving circuit that receives and processes these data separately, eliminating the need for large-capacity external RAM by using time division multiplexing and dedicated transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large-capacity external compensation RAM memory is used to store correction data for high-resolution displays, then the image correction processing capability is improved, but the chip size increases and manufacturing cost increases
Solution Approach 1:
The memory is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can be independently accessed. Different correction data for different display regions or purposes are stored in different banks, allowing parallel access and reducing the need for a single large memory block, thus reducing overall chip size while maintaining large storage capacity.
Solution Approach 2:
The patent transitions from a single large external RAM to a multi-dimensional memory structure with multiple banks organized in a matrix. This allows data to be accessed from multiple dimensions simultaneously, effectively increasing storage capacity without proportionally increasing chip area.
2Quantity of substance
If a large-capacity external compensation RAM memory is used to store correction data for high-resolution displays, then the image correction processing capability is improved, but the manufacturing cost increases
Solution Approach 1:
The memory is divided into multiple banks (first bank, second bank, third bank, fourth bank) that can be independently accessed. Different correction data for different display regions or purposes are stored in different banks, allowing parallel access and reducing the need for a single large memory block, thus reducing overall chip size while maintaining large storage capacity.
Solution Approach 2:
The patent transitions from a single large external RAM to a multi-dimensional memory structure with multiple banks organized in a matrix. This allows data to be accessed from multiple dimensions simultaneously, effectively increasing storage capacity without proportionally increasing chip area.
3Productivity
If correction data and image signal data are transmitted through separate paths, then the image correction processing efficiency is improved, but the device complexity increases
Solution Approach 1:
The transmission system is segmented into multiple independent paths: a first transmission path for image signal data and a second transmission path for correction data. Each path has dedicated input ports and processing circuits, allowing simultaneous independent processing without interference, thus improving overall processing efficiency.
Solution Approach 2:
The display driving circuit is designed with multi-functional capabilities to handle both image signal processing and correction data processing through different paths. The circuit can selectively process different types of data through appropriate input ports and processing circuits, achieving universal functionality without requiring separate dedicated systems for each function.
Data Source
AI summary
The present disclosure provides a processor, a display driving circuit, and an electronic device. The processor includes: a memory being divided into a first part that stores correction data for correcting an image signal, a second part that stores data of an image signal to be displayed, and a third part that stores data of an application to be executed; and an output port configured to transmit the data of the image signal and the correction data stored in the memory to an external display driving circuit, separately.