Processor Memory Slice Architecture for Metadata-Free Data Flow
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Solution Overview
Problem
Existing processor designs face inefficiencies due to latency caused by instruction decoding and data retrieval from cache or memory, which hinders overall execution performance.
Innovation Solution
A processor with a functional slice architecture is introduced, where tiles are organized into slices for specific functions, allowing data and instruction flows to occur in perpendicular directions, synchronized by a compiler aware of the hardware configuration, eliminating the need for metadata and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If data is transmitted between memory tiles and functional slices with metadata indicating operations, then operational clarity is improved, but data transmission efficiency deteriorates due to increased bandwidth requirements
Solution Approach 1:
Each memory tile and functional slice is equipped with timing circuits and control logic that automatically generate and process timing signals. The system self-regulates data flow timing without requiring external metadata, as each component independently determines when to sample or transmit data based on shared clock cycles and timing signals.
Solution Approach 2:
The patent changes the parameter of data transmission from including metadata to using timing-based control. By transforming the control mechanism from content-based (metadata indicating operations) to time-based (specific clock cycles for data arrival), the system eliminates metadata overhead while maintaining operational clarity through synchronized timing.
2Measurement precision
If instructions and data are processed sequentially through traditional decoding stages, then processing accuracy is improved, but execution speed deteriorates due to latency
Solution Approach 1:
The compiler performs preliminary actions by pre-determining the exact timing for data arrival at each functional slice during the compilation stage. By pre-calculating and encoding timing information into the instruction stream, the runtime system can execute operations immediately when data arrives at the predetermined time, eliminating sequential decoding latency while maintaining accuracy through compiler-verified timing relationships.
Solution Approach 2:
The patent introduces a time dimension to the instruction-execution model. Instead of sequential processing through multiple decoding stages, the system uses parallel execution across multiple clock cycles where each cycle corresponds to a specific timing relationship between data arrival and operation execution. This temporal dimensionality allows simultaneous processing of multiple operations at different stages of the pipeline.
3Reliability
If metadata is included with operand data to indicate operations, then operational correctness is improved, but device complexity deteriorates due to additional processing requirements
Solution Approach 1:
Functional slices contain built-in timing detection circuits that automatically determine the operation type based on when data arrives relative to the instruction timing. Each functional slice independently monitors its own input timing and self-determines what operation to perform, eliminating the need for external metadata interpretation logic and reducing overall system complexity.
Solution Approach 2:
The patent replaces the mechanical system of metadata transmission and interpretation with a timing-based control mechanism. Instead of transmitting operation codes as data bits that require decoding logic, the system uses the temporal relationship between instruction issuance and data arrival to encode operation information, substituting complex decoding circuitry with simpler timing synchronization logic.
Data Source
AI summary
A processor having a functional slice architecture is divided into a plurality of functional units (“tiles”) organized into a plurality of slices. Each slice is configured to perform specific functions within the processor, which may include memory slices (MEM) for storing operand data, and arithmetic logic slices for performing operations on received operand data. The tiles of the processor are configured to stream operand data across a first dimension, and receive instructions across a second dimension orthogonal to the first dimension. The timing of data and instruction flows are configured such that corresponding data and instructions are received at each tile with a predetermined temporal relationship, allowing operand data to be transmitted between the slices of the processor without any accompanying metadata. Instead, each slice is able to determine what operations to perform on received data based upon the timing at which the data is received.