Processor Memory Switching for CAN Start-Up Speed
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Solution Overview
Problem
Devices connected to controller area networks (CANs) face challenges in quickly transitioning from a powered-off state to a communicative state within a specified start-up period, as existing methods either suffer from slow operational speed when executing directly from non-volatile memory or are unable to meet timing constraints when copying binaries to volatile memory.
Innovation Solution
A system utilizing a non-volatile memory with a binary section, a first page table, and a second page table, where a processor initializes using the first page table, copies the binary section to volatile memory, and then switches to using the second page table for execution, allowing seamless transition and faster operation from volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor executes directly from non-volatile memory, then the device can quickly power up and meet timing constraints, but the operational speed is slow
Solution Approach 1:
The binary section is pre-loaded into the volatile memory during the initialization phase before the processor begins executing instructions. This preliminary action allows the processor to switch from slow non-volatile memory execution to fast volatile memory execution without waiting for the entire binary to be copied, thus resolving the contradiction between start-up time and operational speed.
2Speed
If the processor copies the binary section from non-volatile memory to volatile memory before execution, then the operational speed improves, but the start-up time increases
Solution Approach 1:
The copying of the binary section from non-volatile memory to volatile memory begins during the initialization phase, before the processor needs to execute instructions. This preliminary copying action is performed in parallel with other initialization tasks, allowing the processor to start executing from the copied binary in volatile memory without waiting for the entire copy operation to complete, thus resolving the contradiction between operational speed and start-up time.
Solution Approach 2:
Only the critical binary section required for immediate execution is copied to volatile memory, rather than copying the entire memory content. This partial action approach minimizes the copying time and allows the processor to quickly transition to fast execution mode, resolving the contradiction between operational speed improvement and start-up time penalty.
3Adaptability or versatility
If the device uses a single page table for execution, then the memory management is simple, but it cannot support seamless switching between non-volatile and volatile memory execution
Solution Approach 1:
The memory management structure is segmented into two separate page tables: a first page table for managing non-volatile memory execution and a second page table for managing volatile memory execution. This segmentation allows the processor to switch between different memory types by switching between page tables, providing the adaptability needed to resolve the contradiction between execution flexibility and system complexity.
Data Source
AI summary
Described examples include a system having a non-volatile memory including a binary section, a first page table and a second page table. The system also has a volatile memory and a processor coupled to the non-volatile memory and the volatile memory, the processor operable to use the first page table when the processor is initialized, the first page table including a first pointer to the binary section, the processor operable to cause copying of the binary section of the non-volatile memory to the volatile memory to create a copied binary section in the volatile memory, and the processor operable to use the second page table when the copying is complete, the second page table including a second pointer to the copied binary section.