Reconfigurable Processor Memory Allocation for Tensor Access Conflicts

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Solution Overview

Problem

Memory unit management in reconfigurable dataflow computing systems significantly affects performance, and existing technologies struggle to efficiently allocate and dispatch tensor data to physical memory units in a manner that optimizes resource utilization and minimizes conflicts.

Innovation Solution

A data processing system comprising reconfigurable units with pattern compute and memory units, utilizing a compiler to create duplicate tensors, assign contexts, trim unnecessary portions, and dispatch assigned contexts to PMUs, ensuring no duplicate tensor exceeds its I/O port capacity, thereby optimizing memory allocation and reducing conflicts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single tensor is dispatched directly to memory units, then the memory allocation process is simple, but resource conflicts occur when multiple contexts of the same type need to access the same tensor simultaneously

Engineering Contradiction:
Improvememory access conflict resolutionVSAvoidtensor duplication and assignment mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the single tensor into multiple duplicate tensors, where each duplicate is assigned to specific contexts. This segmentation allows independent access to different tensor copies by different contexts, eliminating conflicts while maintaining manageable complexity through systematic duplication strategies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of tensor duplication where instead of a single tensor serving all contexts, multiple tensor copies are created in a expanded tensor space. This dimensional expansion allows parallel access paths for different contexts without interference, resolving the conflict-resolution complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If duplicate tensors are created for each memory access pattern, then resource conflicts are eliminated, but memory utilization efficiency decreases due to redundant data

Engineering Contradiction:
Improvememory access conflict resolutionVSAvoidmemory data volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by creating duplicate tensors selectively based on specific access patterns and contexts rather than uniformly duplicating all data. Each duplicate is tailored to specific read/write contexts, optimizing memory utilization by duplicating only when and where conflicts occur, rather than creating redundant copies for all possible access scenarios.

Inventive Principle:
Principle #3Local quality

3Productivity

If all memory access patterns are assigned to the same tensor, then device complexity is minimized, but the number of simultaneous memory operations is limited by I/O port capacity

Engineering Contradiction:
Improveconcurrent memory operationsVSAvoidtensor duplication and assignment mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments memory access patterns into different groups based on their I/O port requirements and conflict characteristics. By creating duplicate tensors for different access pattern groups, the system enables parallel memory operations limited only by physical I/O port capacity rather than being constrained by a single tensor's access sequence.

Inventive Principle:
Principle #1Segmentation

4Quantity of substance

If tensors are trimmed to retain only necessary portions, then memory utilization efficiency improves, but the complexity of determining necessary portions increases

Engineering Contradiction:
Improvememory data volumeVSAvoidtensor trimming and selection logic
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing tensor trimming and selection during the compilation phase before runtime execution. The compiler analyzes memory access patterns and pre-determines which tensor portions are necessary for each context, creating optimized duplicate tensors in advance. This eliminates the need for complex runtime trimming logic while maintaining memory efficiency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260064599A1Memory allocation in a reconfigurable data processor
Publication Date: 2026.03.05 SAMBANOVA SYSTEMS INC
  • US20260064599A1 patent drawing
  • US20260064599A1 patent drawing
  • US20260064599A1 patent drawing

AI summary

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor.