Processor Memory Data Transfer Stall Reduction
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Solution Overview
Problem
Existing computer systems face performance bottlenecks due to the stalling of processor execution when performing data transfer operations, as the processor cannot simultaneously fetch instructions and access data from the same memory.
Innovation Solution
The method involves moving load and store instructions from the source memory to the destination memory, allowing the processor to execute these instructions without stalling by accessing different memory locations in each clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the processor fetches instructions and accesses data from the same memory in the same clock cycle, then the memory access is simplified, but the processor execution stalls due to resource conflict
Solution Approach 1:
The patent divides the memory access operations into separate segments: instruction fetch and data access are performed in different clock cycles. The processor first fetches instructions in one clock cycle, then accesses data from memory in the subsequent clock cycle, eliminating the resource conflict that causes stalls.
Solution Approach 2:
The patent introduces dynamic timing adjustment where the processor adapts its operation sequence based on the specific instruction being executed. For instructions requiring both fetch and data access, the processor dynamically schedules these operations in separate clock cycles rather than attempting simultaneous execution.
2Reliability
If the processor completes data transfer in multiple clock cycles to avoid stalls, then resource conflicts are resolved, but the execution time increases
Solution Approach 1:
The patent performs preliminary action by pre-fetching instructions into an instruction buffer before they are needed for execution. This allows the processor to have instructions ready in advance, reducing the overall execution time while maintaining reliable operation without stalls.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping instruction fetch and data access operations across different clock cycles. While one operation is performed, the processor prepares for the next operation, ensuring that the pipeline remains active and minimizing idle time between operations.
Data Source
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AI summary
A method and system (100) for moving data from a source memory (102) to a destination memory (104) by a processor (106) are disclosed. The processor (106) has a plurality of registers (114) and the source memory (102) stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor (106) moves the load instructions from the source memory (102) to the destination memory (104). Then, the processor (106) initiates execution of the load instructions from the destination memory (104) in order to load the data from the source memory (102) to one or more registers (114) in the processor (106). Execution then returns to the sequence of instructions stored in the source memory (102), and the processor (106) stores the data from the registers (114) to the destination memory (104).