Processor Micro Cache Architecture for Instruction Throughput
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Solution Overview
Problem
Existing processors face limitations in processing ability and power consumption due to the need to repeatedly read instructions from external memory, even for frequently executed instructions, which increases power usage and reduces efficiency.
Innovation Solution
A processor configuration that includes an instruction cache and a micro cache, allowing the core to process multiple micro instructions simultaneously by converting and outputting third instructions of 32 bitwidth from the micro cache during a micro instruction mode, enabling simultaneous processing of frequently executed instructions in a single cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If instructions are sequentially read from external memory, then the processor can execute instructions in order, but the processing speed is limited and power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-fetching and storing multiple instructions in the instruction cache before they are needed. The instruction cache holds frequently executed instructions ready for immediate access, eliminating the need to repeatedly access external memory for the same instructions, thus reducing power consumption and improving processing speed.
Solution Approach 2:
The patent introduces an instruction cache as an intermediary between the external memory and the processor core. This intermediary layer stores copies of frequently used instructions, allowing the core to access them quickly without directly accessing external memory, thereby reducing power consumption and increasing instruction processing speed.
2Speed
If the cache stores all frequently used instructions, then access speed improves, but the cache size and complexity increase
Solution Approach 1:
The patent segments the caching system into two distinct parts: an instruction cache for storing instruction copies and a micro cache for storing expanded micro-instructions. This segmentation allows each cache to be optimized for its specific purpose, managing complexity while maintaining high access speeds.
Solution Approach 2:
The patent adds a new dimension to the caching system by introducing the micro cache layer that expands single instructions into multiple micro-instructions. This dimensional addition allows the system to handle complex instructions efficiently without significantly increasing the base instruction cache size, thus improving access speed while managing complexity.
3Productivity
If multiple instructions are processed simultaneously in a single cycle, then processing ability improves, but the instruction format and execution complexity increase
Solution Approach 1:
The patent segments instructions into micro-instructions that can be executed in parallel. By breaking down complex instructions into smaller, simpler micro-instructions stored in the micro cache, the system can process multiple instructions simultaneously in a single cycle, increasing throughput while managing execution complexity through structured decomposition.
Solution Approach 2:
The patent implements dynamic instruction expansion where single instructions are converted into multiple micro-instructions based on the specific instruction type and requirements. This dynamic approach allows the system to optimize for parallel processing when beneficial, increasing productivity while maintaining flexibility to handle different instruction complexities as needed.
Data Source
AI summary
The present invention relates to a processor including: an instruction cache configured to store at least some of first instructions stored in an external memory and second instructions each including a plurality of micro instructions; a micro cache configured to store third instructions corresponding to the plurality of micro instructions included in the second instructions; and a core configured to read out the first and second instructions from the instruction cache and perform calculation, in which the core performs calculation by the first instructions from the instruction cache under a normal mode, and when the process enters a micro instruction mode, the core performs calculation by the third instructions corresponding to the plurality of micro instructions provided from the micro cache.