Processor Mode Switching via Address Least Significant Bits
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Solution Overview
Problem
Existing processor architectures face challenges in efficiently tracking and switching between execution modes, such as ARM and THUMB modes, due to limitations in using the least significant bit of the program counter, which complicates software and hardware implementations and requires additional operations like adding '1' for mode switching, leading to increased complexity and hardware costs.
Innovation Solution
The solution involves using the least significant bits of addresses of called functions to switch between execution modes by defining a 'classic' aligned mode and a 'compressed' unaligned mode, where selected instructions are forcibly misaligned to indicate mode changes, allowing the processor to determine mode switches based on these bits without relying on reserved bits or additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the least significant bit of the program counter is used to store the mode bit, then mode tracking is achieved, but the LSB is no longer part of the actual address and alignment restrictions are imposed
Solution Approach 1:
The patent divides the mode tracking function into two parts: the upper bits of the PC store the actual address, while the least significant bit serves as the mode indicator. This segmentation allows the PC to simultaneously hold both address information and mode information without requiring separate storage mechanisms.
Solution Approach 2:
The least significant bit of the PC is made multi-functional: it serves as both part of the address space (enabling odd-addressed instructions in THUMB mode) and as a mode indicator. This eliminates the need for separate mode storage and allows flexible addressing in both ARM and THUMB modes.
2Reliability
If addition of '1' is required for every jump to THUMB mode, then mode switching is achieved, but software complexity increases
Solution Approach 1:
The patent makes the mode switching process self-service by using the least significant bit of the target address itself to indicate the desired mode. The processor automatically determines the mode by examining this bit without requiring external software intervention or special handling by the linker.
Solution Approach 2:
The patent changes the parameter used for mode indication from a separate mode bit (requiring addition operations) to the least significant bit of the target address. This parameter change allows mode information to be embedded directly in the address, eliminating the need for additional operations during mode switching.
3Ease of operation
If the LSB is used to represent the mode, then mode tracking is simplified, but alignment restrictions require nop instructions
Solution Approach 1:
The patent introduces dynamic alignment requirements: instructions in THUMB mode can be placed at odd addresses (LSB=1) when in compressed mode, eliminating the need for static 16-bit alignment. This dynamic approach allows the processor to adapt to different alignment scenarios without requiring corrective nop instructions.
Solution Approach 2:
The patent changes the alignment parameter from fixed 16-bit boundaries to flexible boundaries determined by the least significant bit of the address. This allows instructions to be placed at any address, with the LSB automatically indicating the mode, thereby eliminating the need for alignment-correcting nop instructions.
4Reliability
If reserved bits are used for mode indication, then mode tracking is achieved, but hardware costs increase
Solution Approach 1:
The patent makes the least significant bit of the PC multi-functional, using it both as part of the address space and as a mode indicator. This eliminates the need for dedicated reserved bits or separate mode storage registers, thereby reducing hardware requirements and costs.
Solution Approach 2:
The processor uses its existing PC register self-service for mode tracking by examining the least significant bit of the target address. This eliminates the need for additional hardware components or reserved bits dedicated to mode indication, as the PC itself provides both addressing and mode information.
Data Source
AI summary
Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.