Multi-Processor Mode Switching for Power and Performance
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Solution Overview
Problem
Current multi-processing systems face challenges in efficiently switching between symmetric multi-processing (SMP) and asymmetric multi-processing (ASMP) modes, leading to higher power consumption and performance issues due to unbalanced workloads and fixed clock frequencies/voltages in SMP systems, while ASMP systems are more power-efficient but complex and costly.
Innovation Solution
A multi-processing system that can dynamically switch between SMP and ASMP modes by controlling clock frequencies and voltages, using a controller and clock switching circuit to enable glitchless transitions, allowing for real-time mode selection based on workload and power consumption, thereby minimizing software intervention and optimizing performance and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SMP mode is used with fixed clock frequencies and voltages, then system simplicity is maintained, but power consumption increases due to unbalanced workloads
Solution Approach 1:
The system dynamically switches between SMP and ASMP modes based on workload conditions. A mode selection mechanism monitors system state and transitions between symmetric and asymmetric processing configurations, allowing the system to adapt its complexity and power consumption characteristics to match actual computational demands rather than being fixed in one configuration.
Solution Approach 2:
The invention changes the operational parameters of the multi-processor system by adjusting clock frequencies and voltage levels individually for each processor core. This allows the system to optimize power consumption by running cores at lower frequencies/voltages when they are idle or under light load, while maintaining higher performance for active cores handling heavy workloads.
2Use of energy by moving object
If ASMP mode is used with individually scalable clock frequencies, then power efficiency improves, but hardware complexity and cost increase
Solution Approach 1:
The system implements a universal multi-processor platform that can operate in both SMP and ASMP modes. The same hardware infrastructure supports both symmetric and asymmetric processing configurations, eliminating the need for separate hardware designs for each mode. This reduces overall hardware complexity while maintaining the power efficiency benefits of ASMP when needed.
Solution Approach 2:
The system dynamically configures its operational mode between SMP and ASMP based on workload requirements. This dynamic adaptability allows the system to achieve ASMP power efficiency benefits only when asymmetric processing is actually needed, rather than maintaining complex ASMP hardware that would be underutilized during balanced workload scenarios.
3Use of energy by moving object
If ASMP mode is used with different clock frequencies for processors and L2 cache, then power consumption decreases, but latency increases when L1 cache miss rate is high
Solution Approach 1:
The system dynamically adjusts the clock frequency relationship between processors and L2 cache based on operational conditions. When L1 cache miss rates are high and frequent L2 access is required, the system increases the L2 cache clock frequency relative to processor frequency to reduce access latency. When L1 cache performance is good and power savings are prioritized, the L2 cache operates at lower frequencies.
Solution Approach 2:
The invention implements dynamic frequency scaling for the L2 cache relative to processor frequencies. This allows the system to optimize the balance between power consumption and access latency in real-time based on actual cache performance metrics and workload characteristics, rather than using a fixed frequency relationship.
4Device complexity
If SMP mode is used with shared L2 cache, then hardware simplicity is maintained, but performance suffers due to unbalanced processor workloads
Solution Approach 1:
The system dynamically switches between shared L2 cache (SMP mode) and individually scalable L2 cache configurations (ASMP mode) based on workload balance. When processor workloads are balanced, the simpler shared cache configuration is used. When workloads become unbalanced, the system transitions to ASMP mode with individually configurable cache resources to match each processor's actual demand, optimizing overall system performance.
Solution Approach 2:
The invention changes the cache allocation parameters dynamically, transitioning from a fixed shared L2 cache configuration to individually scalable cache configurations. This allows the system to optimize cache resources per processor based on actual workload requirements, improving performance for unbalanced workloads while maintaining hardware simplicity for balanced scenarios.
Data Source
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AI summary
A processing system with multiple processors is switchable between two modes of operation dynamically: symmetrical multi-processing (SMP) and asymmetrical multi-processing (ASMP). The system uses certain criteria to determine when to switch to improve the power consumption or performance. A controller enables control and fast-switching between the two modes. Upon receipt of a switching command to switch between SMP and ASMP, a series or sequence of actions are performed to control voltage supplies and CPU/memory clocks to the multiple processors and cache memory.