Processor Mode Switching via Identity-Mapped Page Tables
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Solution Overview
Problem
Current virtualization systems face challenges in efficiently switching between different operating modes of a processor, particularly when transitioning between 64-bit and legacy modes, which limits the ability to run multiple operating systems simultaneously on 64-bit hardware platforms.
Innovation Solution
A method is introduced for switching between software entities executing in different processor modes by using a switch page table with identity mappings, disabling and enabling memory paging, and modifying the processor mode, allowing for seamless transitions between 64-bit and legacy modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a processor runs in a single operating mode (either 64-bit or legacy mode), then the system architecture is simple and easy to manage, but the system cannot run multiple operating systems with different architecture requirements simultaneously
Solution Approach 1:
The processor dynamically switches between 64-bit mode and legacy mode based on the requirements of different virtual machines. The mode switching is triggered by virtual machine context switches, allowing the system to adapt to different operating system architecture requirements while running multiple OSes concurrently on the same hardware platform
Solution Approach 2:
A virtual machine monitor (VMM) acts as an intermediary layer between the physical processor and multiple virtual machines. The VMM manages processor mode switching by intercepting mode switch instructions, saving/restoring processor state, and coordinating the transition between 64-bit and legacy modes, thereby enabling multiple OSes with different architecture requirements to run simultaneously
2Speed
If memory paging is always enabled for virtual memory management, then memory protection and virtual addressing work correctly, but the overhead of page table translations reduces processing speed
Solution Approach 1:
Memory paging is temporarily disabled during the brief period when processor mode switching occurs, and then re-enabled after the switch is complete. This periodic disabling and enabling of paging allows the system to perform mode switches without the overhead of continuous page table translations, while still maintaining memory management correctness during normal operation
Solution Approach 2:
Before switching processor modes, the system preliminarily saves the current page table base register value and prepares the new page table configuration. This preliminary preparation ensures that when paging is re-enabled after the mode switch, the correct page tables are already in place, maintaining memory management correctness without requiring paging to remain enabled during the transition
Data Source
AI summary
A processor has multiple operating modes, such as the long/compatibility mode, the long/64-bit mode and the legacy modes of the x86-64 microprocessor. Different software entities execute in different ones of these operating modes. A switching routine is implemented to switch from one operating mode to another and to transfer control from one software entity to another. The software entities may be, for example, a host operating system and a virtual machine monitor. Thus, for example, a virtual computer system may comprise a 64-bit host operating system and a 32-bit virtual machine monitor, executing on an x86-64 microprocessor in long mode and legacy mode, respectively, with the virtual machine monitor supporting an x86 virtual machine. The switching routine may be implemented partially or completely in an identity-mapped memory page. Execution of the switching routine may be initiated by a driver that is installed in the host operating system of a virtual computer system.