Processor Module Data Exchange Synchronization
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Solution Overview
Problem
In multi-threaded and multi-tiled processing systems, existing technologies face challenges in synchronizing data exchanges between processor modules without relying on deterministic timing, particularly in non-time-deterministic interconnects, which can lead to complexity and inefficiency, especially across different chips or tiles.
Innovation Solution
A processing system is implemented with multiple processor modules that operate in bulk synchronous parallel (BSP) supersteps, using a non-time-deterministic interconnect for data exchange between different sets of processor modules, where each module performs computations and exchanges results in alternating phases with barrier synchronization, and employs a pre-programmed counter to ensure synchronized data finalization without needing to know the timing of incoming data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deterministic timing is used for data exchange synchronization between processor modules, then synchronization reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent introduces a barrier synchronization mechanism as an intermediary that mediates data exchange between processor modules. Instead of direct deterministic timing coordination between modules, the barrier acts as a centralized coordinator that collects completion signals from all modules and manages the synchronization state, thereby reducing the complexity of direct inter-module timing coordination while maintaining synchronization reliability
Solution Approach 2:
Each processor module autonomously manages its own synchronization state by locally maintaining a completion counter that tracks exchanged data elements. The module independently decrements its counter as data arrives and automatically proceeds when the counter reaches zero, eliminating the need for complex centralized timing control and reducing overall system complexity while ensuring reliable synchronization
2Measurement precision
If deterministic timing is used for data exchange synchronization, then synchronization precision is improved, but power consumption increases
Solution Approach 1:
The system employs periodic barrier synchronization events rather than continuous deterministic timing monitoring. Processor modules operate independently during compute phases, then periodically synchronize at barrier points where data exchange completion is confirmed. This periodic approach maintains precise synchronization at critical points while allowing modules to consume minimal power during independent execution phases
Solution Approach 2:
Each processor module autonomously tracks its data exchange completion status using a local counter, eliminating the need for continuous power-consuming centralized timing signals. The module only consumes additional power when actually exchanging data or reaching a barrier synchronization point, rather than maintaining constant synchronization overhead
3Adaptability or versatility
If non-time-deterministic interconnect is used for data exchange, then adaptability is improved, but synchronization reliability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where receiving processor modules send completion signals back to the barrier synchronization mechanism as data elements arrive. The barrier uses this feedback to track when all expected data has been received from all processor modules, and only then allows progression to the next compute phase. This feedback loop ensures reliable synchronization even though the underlying interconnect is non-time-deterministic
Solution Approach 2:
The barrier synchronization mechanism serves as an intermediary that shields processor modules from the non-time-deterministic nature of the interconnect. Modules simply exchange data and signals through the barrier, which manages the complexity of tracking all data arrivals and coordinating synchronization, thereby maintaining reliability while allowing flexible non-deterministic communication underneath
4Reliability
If barrier synchronization is implemented for all processor modules, then synchronization reliability is improved, but device complexity increases
Solution Approach 1:
The barrier synchronization mechanism is segmented and distributed across multiple processor modules rather than being a single centralized complex unit. Each module maintains its own completion counter and independently tracks data arrivals, dividing the synchronization management task into simple local functions. This segmentation reduces the complexity of any single component while collectively achieving reliable system-wide synchronization
Solution Approach 2:
Each processor module autonomously manages its own synchronization state without requiring complex centralized control. The module independently counts incoming data elements, decrements its counter as data arrives, and automatically determines when synchronization is complete. This self-service approach distributes the synchronization logic across simple local units rather than requiring a complex centralized barrier mechanism
Data Source
AI summary
A processing system comprising: multiple processor modules, each comprising a respective execution unit memory; and an interconnect for exchanging data between different sets of the processor modules. A group of the processor modules operates in a series of steps. For an exchange phase of each step by each receiving processor module that is to receive data from outside its own set, the receiving module is pre-programmed with a value representing the number of units of data to receive. Starting from the pre-programmed value, it then counts out the number of data units remaining to be received each time a data unit is received. Each receiving processor module is further arranged to perform an exchange synchronization whereby, before advancing from the exchange phase to the compute phase of the current step, the receiving processor module waits until no units of data remain to be received according to the count.