Processor Multiplier Merging Partial Products
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Solution Overview
Problem
High-performance processors face challenges in efficiently multiplying large bit-width numbers due to high power consumption and heat dissipation, which affects performance and reliability, especially in complex multiplier circuits used for signal processing.
Innovation Solution
A method and apparatus for multiplying a 64-bit multiplier and multiplicand by merging partial product subsets over four cycles using Booth encoding, feedback sum, and carry results, with logic inputs selected cyclically to efficiently compress and generate the product, employing a Booth encoder, partial product generator, compressors, storage devices, logic gates, and an adder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a parallel multiplier circuit with a large number of compressors is used for large bit-width multiplications, then the multiplication speed is improved, but the power consumption and heat dissipation increase
Solution Approach 1:
The patent divides the multiplication process into multiple cycles, with each cycle handling a subset of partial products. Instead of computing all partial products simultaneously in a single parallel stage, the circuit processes them in sequential batches, reducing the number of active compressors at any given time and thereby lowering power consumption while maintaining overall multiplication speed.
Solution Approach 2:
The patent employs periodic action by organizing the multiplication into discrete cycles where different subsets of partial products are processed in alternating time periods. This periodic processing allows the circuit to activate only the necessary compressors for each cycle, reducing simultaneous switching activity and dynamic power consumption compared to a fully parallel approach.
2Speed
If a parallel multiplier circuit with a large number of compressors is used for large bit-width multiplications, then the multiplication speed is improved, but the heat dissipation increases
Solution Approach 1:
By segmenting the partial product processing into multiple cycles with smaller subsets, the patent reduces the number of compressors operating simultaneously. This segmentation directly reduces the instantaneous heat generation from simultaneous switching and computation, making heat dissipation more manageable while still achieving high overall multiplication throughput through efficient cycle utilization.
Solution Approach 2:
The periodic processing of partial product subsets distributes heat generation over time rather than concentrating it in a single parallel stage. This temporal distribution of computational workload allows heat to dissipate between cycles, preventing thermal accumulation and improving reliability without sacrificing multiplication speed.
3Speed
If higher order compressors are configured to reduce vertical critical paths, then the product is generated faster, but the device complexity increases
Solution Approach 1:
The patent employs dynamic compressor configuration where the order and activation of compressors change from cycle to cycle based on which subset of partial products is being processed. This dynamic reconfiguration allows the use of higher-order compressors when beneficial for speed while keeping the overall system manageable through systematic control logic that adapts the compressor usage pattern to current computational needs.
Data Source
AI summary
A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand.