Processor Network-on-Chip Coherency Management
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Solution Overview
Problem
In integrated circuits, maintaining coherency between cache and common memory is challenging due to cache misses and outdated data, especially with multiple processor cores accessing shared memory, leading to inefficiencies and potential data inconsistencies.
Innovation Solution
Implementing processor and network-on-chip coherency management through a coherent network-on-chip that enables global coherency, with local caches shared among processor cores operating under local coherency, and performing cache maintenance operations to generate coherency transactions between global and local coherency, ensuring data consistency across multiple processor cores and caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If local caches are shared among processor cores with local coherency, then processing speed is improved by reducing cache misses, but data consistency between local caches and global memory deteriorates
Solution Approach 1:
The system divides coherency management into two segments: local coherency within groups of processor cores sharing a local cache, and global coherency across the entire system through the network-on-chip. This segmentation allows fast local access while maintaining global consistency through controlled interfaces between local and global coherency domains.
Solution Approach 2:
The network-on-chip acts as an intermediary between local caches and global memory, mediating coherency transactions. It receives coherency requests from local caches, performs the necessary global coherency operations, and returns results, thereby maintaining data consistency without requiring direct access to all memory resources by each cache.
2Reliability
If multiple processor cores access shared memory through a coherent network-on-chip, then global coherency is maintained, but access conflicts and inefficiencies increase
Solution Approach 1:
Processor cores are organized into groups, with each group having a dedicated local cache. This segmentation reduces the number of cores competing for access to the same memory resources, thereby reducing access conflicts while maintaining global coherency through the network-on-chip.
Solution Approach 2:
Each local cache is optimized for its specific group of processor cores, providing fast local access tailored to the needs of that group. This local optimization improves access efficiency for local operations while the global coherency mechanism handles cross-group access requirements.
3Reliability
If cache maintenance operations are performed to generate coherency transactions, then data integrity is ensured, but system overhead increases
Solution Approach 1:
Cache maintenance operations are performed proactively to maintain coherency before data inconsistencies arise. By anticipating coherency requirements and performing maintenance operations in advance, the system ensures data integrity without requiring expensive reactive corrections, thereby reducing overall system overhead.
Solution Approach 2:
The coherency management system uses feedback from coherency transactions to determine when maintenance operations are needed. This feedback-driven approach ensures that cache maintenance is performed only when necessary to maintain data integrity, optimizing the balance between reliability and overhead.
Data Source
AI summary
Techniques for coherency management based on processor and network-on-chip coherency management are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores accesses a common memory through a coherent network-on-chip. The coherent network-on-chip comprises a global coherency. A local cache is coupled to a grouping of two or more processor cores. The local cache is shared among the two or more processor cores. The grouping of two or more processor cores and the shared local cache operates using local coherency. The local coherency is distinct from the global coherency. A cache maintenance operation is performed in the grouping of two or more processor cores and the shared local cache. The cache maintenance operation generates cache coherency transactions between the global coherency and the local coherency. The cache coherency transactions enable coherency among the plurality of processor cores, local caches, and the memory.