Processor Power Control via Variable ON-OFF Keying
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Solution Overview
Problem
Current power management techniques for computer systems, such as dynamic voltage and frequency scaling, face inefficiencies due to minimum operating voltage constraints and software inefficiencies, leading to significant energy consumption in computing devices, which necessitate improved energy efficiency and conservation methods.
Innovation Solution
Implementing an ON-OFF keying protocol that periodically places processor components into power-saving states with variable cycle times, adjusting on and off times based on maximum acceptable off times and requested speeds to minimize overhead and maximize efficiency, which can be complementary to other power control methods like voltage-frequency scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling is used to reduce power consumption, then power consumption is reduced, but efficiency suffers because circuits have a minimum operating voltage and cannot operate below it
Solution Approach 1:
The patent applies periodic action by implementing ON-OFF keying that periodically transitions the processor between active and low-power states. This periodic switching allows the system to operate at minimum voltage Fmin with maximum efficiency while reducing average power consumption through controlled idle periods, resolving the contradiction between power reduction and efficiency maintenance
Solution Approach 2:
The patent applies dynamics by making the processor's operational state variable rather than fixed. The system dynamically adjusts between full operation at Fmin and low-power states based on workload requirements, allowing optimal efficiency during active periods while achieving power reduction during idle periods, thus resolving the contradiction between maintaining efficiency and reducing power consumption
2Use of energy by moving object
If software-generated requests for idle states are used without direct control of voltage, then power consumption is reduced, but there is no guarantee of the physical state that will result
Solution Approach 1:
The patent applies self-service by implementing hardware-based voltage and frequency control that automatically maintains the processor at the optimal Fmin operating point without requiring software intervention. The hardware directly controls the physical state to ensure it remains at the most efficient operating point, providing both power reduction and reliable state guarantee simultaneously
3Use of energy by moving object
If speed is reduced below Fmin to reduce power, then power consumption is reduced, but speed drops faster than power so efficiency suffers
Solution Approach 1:
The patent applies periodic action by implementing ON-OFF keying that periodically transitions the processor between active and low-power states. This allows the processor to maintain Fmin speed during active periods (preserving efficiency) while achieving power reduction through controlled idle periods, avoiding the need to operate below Fmin where efficiency deteriorates
Data Source
AI summary
In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.