Processor Operand Storage for Software Pipelined Loops

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Solution Overview

Problem

Existing computer processors face inefficiencies in managing transient operands due to fixed register sizes and waste of hardware resources, particularly in software pipelined loops, where rotating registers are often oversized for vector data and occupied by small operands, leading to increased register pressure and potential register shortages.

Innovation Solution

A computer processor with a logical belt system and execution logic that supports operations like RETIRE, INNER, and LEAVE, allowing for dynamic management of operand storage and retirement, enabling efficient handling of transient operands without the need for a prologue or epilogue in software pipelined loops, and utilizing a scratchpad with rotators for efficient operand storage and retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If rotating registers are used to store operands in software pipelined loops, then operand storage is enabled across iterations, but hardware resources are wasted because registers are oversized for vector data and frequently occupied by small operands

Engineering Contradiction:

Improveoperand storage flexibilityVSAvoidhardware resource waste

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent divides the operand storage system into multiple segments: a small fast register file for transient operands, a larger scratchpad memory for loop-carried variables, and a rotating register space specifically for software-pipelined loop operands. This segmentation allows each storage region to be optimized for its specific purpose, preventing the waste of oversized registers on small data while maintaining fast access for critical operands.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic configuration capabilities where the rotating register space can be selectively enabled or disabled, and the scratchpad memory size and organization can be adjusted based on the specific needs of the software-pipelined loop being executed. This dynamic adaptation allows the system to optimize hardware resource usage for each particular loop pattern rather than being constrained by fixed, oversized register allocations.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If the number of registers is fixed by design, then hardware simplicity is maintained, but register pressure increases and complex code may run out of registers

Engineering Contradiction:

Improveregister allocation simplicityVSAvoidcode execution capacity

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent merges multiple storage resources into a unified operand storage system that includes the fixed register file, expandable scratchpad memory, and rotating register space. This combination allows the system to maintain the simplicity of fixed register allocation for basic operations while providing expanded capacity through the scratchpad and rotating registers when complex software-pipelined loops are executed, effectively resolving the conflict between simplicity and capacity.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If registers are rotated to store loop operands, then software pipelining is enabled, but dead registers are rotated along with live ones, increasing register pressure

Engineering Contradiction:

Improveloop parallelization efficiencyVSAvoidregister pressure overhead

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the loop-carried variables and dead registers from the rotating register space and places them in the scratchpad memory, which does not participate in the rotation. This extraction allows the rotating register space to contain only the live, actively-used operands that need to be rotated between iterations, eliminating the waste of rotating dead registers and reducing register pressure while maintaining software pipelining efficiency.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS9817669B2Computer processor employing explicit operations that support execution of software pipelined loops and a compiler that utilizes such operations for scheduling software pipelined loops

Publication Date: 2017.11.14 MILL COMPUTING

AI summary

A computer processor includes execution logic (having a number of functional units) configured to perform operations that access operand data values stored in a plurality of operand storage elements. Such operand data values include a predefined None operand data value indicative of a missing operand value. The operations include a RETIRE operation specifying a number of operand data values that is intended to be retired in a predefined machine cycle. During execution of the RETIRE operation, zero or more at None operand data values are selectively retired in the predefined machine cycle based on the number of operand data values specified by the RETIRE operation and the number of operand data values to be retired as a result of execution of other operations by the execution logic in the predefined machine cycle. Other aspects and software tools are also described and claimed.