Processor Out-of-Order Completion Without Reorder Buffer
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Solution Overview
Problem
Modern processor circuits face inefficiencies due to the need for reorder buffers to manage out-of-order execution, which consume significant area and power, particularly in mobile applications where power management is critical.
Innovation Solution
Implementing out-of-order completion techniques that allow instructions to update the architectural state without the need for a reorder buffer by ensuring that results are safely used to update the processor state before proceeding, thereby eliminating the requirement for a reorder buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order execution is implemented to improve processor utilization, then execution efficiency is improved, but area and power consumption increase due to reorder buffer requirements
Solution Approach 1:
The patent extracts and eliminates the reorder buffer component from the processor architecture while maintaining out-of-order execution capabilities through alternative completion tracking mechanisms, thereby reducing the processor area without sacrificing execution efficiency
Solution Approach 2:
The patent changes the operational parameters of instruction completion by allowing out-of-order completion of instructions while using modified tracking methods that do not require traditional reorder buffers, thus reducing area while preserving productivity
2Productivity
If out-of-order execution is implemented to improve processor utilization, then execution efficiency is improved, but power consumption increases due to reorder buffer operations
Solution Approach 1:
The patent removes the power-consuming reorder buffer component from the processor while maintaining out-of-order execution through alternative mechanisms, thereby reducing power consumption without compromising execution efficiency
Solution Approach 2:
The patent employs simpler, less power-intensive completion tracking structures that consume less energy compared to traditional reorder buffers, achieving the same functional goal with reduced power usage
3Reliability
If reorder buffers are used to manage out-of-order execution, then instruction completion accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts the reorder buffer component and replaces it with simpler completion tracking mechanisms that maintain instruction completion accuracy through alternative organizational methods, thereby reducing device complexity while preserving reliability
Solution Approach 2:
The patent inverts the traditional approach by allowing out-of-order completion without requiring in-order tracking structures like reorder buffers, using instead simplified mechanisms that track completion independently, thus reducing complexity while maintaining accuracy
Data Source
AI summary
A processor circuit that allows for out-of-order completion of instructions is disclosed. A processor circuit may fetch multiple instructions from a memory circuit. As individual instructions are fetched, the processor circuits checks for any hazards associated with the fetched instructions. Once it has been determined that there are no hazards for a particular instruction, it is issued to one of multiple execution circuits in the processor circuit. The processor circuit can complete instructions in an order in which the instructions finish execution by updating its architectural state with corresponding results of the instructions.