Processor Packetizing Module for Power Management Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In systems with multiple sub-systems, the arbitration mechanism for accessing a power management integrated circuit (PMIC) causes long latency, which hinders low-cost and high-performance power management, especially when multiple sub-systems request power simultaneously.
Innovation Solution
A processor with a packetizing module that combines multiple voltage switching signals into a single packet, which is then sent to a PMIC via a bus only when the bus status changes from busy to ready, eliminating the need for arbitration and reducing the number of command frames required in each transaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an arbitration mechanism is used to manage multiple sub-systems accessing PMIC simultaneously, then the interface cost is minimized, but the latency increases significantly
Solution Approach 1:
The packetizing module performs preliminary action by collecting and packetizing multiple voltage switching signals from different sub-systems before the bus becomes busy. This allows multiple commands to be prepared in advance and transmitted together, eliminating the need for sequential arbitration and significantly reducing latency while maintaining a single interface.
2Device complexity
If multiple voltage switching signals are transmitted sequentially through a single PMIC interface, then the interface structure remains simple, but the number of transactions increases and latency accumulates
Solution Approach 1:
The packetizing module merges multiple voltage switching signals into a single packet structure that can be transmitted together through the PMIC interface. This combining approach reduces the number of separate transactions from multiple sequential commands to a single packet transmission, dramatically improving transaction efficiency while keeping the interface structure simple.
3Ease of manufacture
If a single PMIC interface is used for all sub-systems, then the cost is reduced, but the arbitration mechanism causes long latency
Solution Approach 1:
The packetizing module performs preliminary action by collecting and packetizing multiple voltage switching signals from different sub-systems before the bus becomes busy. This allows multiple commands to be prepared in advance and transmitted together, eliminating the need for sequential arbitration and significantly reducing latency while maintaining a single interface.
Data Source
AI summary
The processor comprises multiple sub-systems. Each sub-system is configured to generate a voltage switching signal. The processor also comprises a packetizing module coupled to the sub-systems. The packetizing module packetizes multiple voltage switching signals generated by the sub-systems to a packet. The processor also comprises a PMIF (power management interface) configured to receive the packet and output the packet.