Arithmetic Processor Page-Table Buffer for Address Translation
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Solution Overview
Problem
The existing page-table walk process in arithmetic processors is inefficient due to the high number of memory lookups required, especially with multilevel page tables, leading to increased execution time and hardware complexity, even with caching mechanisms like L1 caches and prefetch buffers.
Innovation Solution
An arithmetic processor is designed with a request generation circuit, a translation buffer, and a page-table buffer that reduces page-table walk time by efficiently managing virtual and physical addresses, using a controller circuit to handle TLB misses and cache data from multiple levels, thereby minimizing hardware requirements and lookup times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multilevel page table structure is used for address translation, then the ability to manage large virtual address spaces is improved, but the number of memory lookups required increases leading to longer execution time
Solution Approach 1:
The patent applies preliminary action by prefetching page table entries from higher levels of the page table hierarchy before they are actually needed for address translation. The prefetch buffer proactively loads entries based on predicted access patterns, so that when a TLB miss occurs, the required page table data is already available in the buffer, significantly reducing the time penalty of multilevel page table walks.
Solution Approach 2:
The patent segments the page table hierarchy into multiple levels (L0, L1, L2, etc.) with dedicated buffers for each level. Instead of treating the entire page table as a single structure requiring sequential access, each level is independently buffered, allowing parallel preparation of data from different levels and reducing the critical path delay of address translation.
2Loss of time
If traditional caching mechanisms like L1 cache and prefetch buffer are used, then some page table data can be cached, but hardware complexity increases and lookup times are not sufficiently reduced
Solution Approach 1:
The patent merges the functionality of multiple separate caching structures (L1 cache, prefetch buffer, and page table buffers for each level) into a unified hierarchical buffering system. This integration eliminates redundant hardware components and control logic that would exist if these structures operated independently, while maintaining the performance benefits of having data from multiple levels readily available.
Solution Approach 2:
The patent creates a universal buffering structure that serves multiple functions: it acts as a cache for recently accessed page table entries, a prefetch buffer for anticipated accesses, and a hierarchical storage system for data from different page table levels. This multi-functional design reduces the need for separate specialized hardware for each function, thereby reducing overall complexity.
3Productivity
If page table data is stored in separate buffers for each level, then lookup efficiency is improved, but hardware resources and device complexity increase
Solution Approach 1:
The patent introduces a buffer management unit that acts as an intermediary between the multiple level-specific buffers and the TLB. This mediator coordinates data movement between buffers, manages buffer contents, and provides a unified interface for address translation operations. By centralizing control logic in this intermediary component, the patent avoids the need for complex distributed control logic that would be required if each buffer managed itself independently.
Data Source
AI summary
An arithmetic processor includes a request generation circuit which generates an information request including a request address. A translation buffer associates a virtual address of a page with a physical address (PA). A page-table buffer associates data in a page table in a level other than the last level with a PA of the data, and stores the associated data and address. A controller circuit obtains, from the request address, a PA of data in a page table to be accessed when the request address is not stored in the translation buffer. The controller circuit searches in the page-table buffer for the data when the page table to be accessed is in a level other than the last level. The controller circuit obtains the data from a memory, such as a cache memory or a main memory, when the page table to be accessed is in the last level, and registers the data in the translation buffer. The translation buffer may output an erase signal to invalidate all entries in the page-table buffer. The page-table buffer may include a control queue which outputs a control signal indicating a least recently used (LRU) entry.