Processor Parameter Passing via Direct Memory Configuration
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Solution Overview
Problem
The conventional method of passing parameters between processors in Software Defined Radio technology using port registers or dual-port RAM leads to high power consumption and reduced efficiency due to cycle delays and the need for external hardware.
Innovation Solution
A method and system where a static configuration parameter is directly introduced and configured in the target program of a slave processor by a master processor using relative addresses, eliminating the need for external hardware like dual-port RAM or registers, and utilizing Direct Memory Access (DMA) mode for parameter transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Mailbox mechanism using port registers or dual-port RAM is used to pass parameters between processors, then parameter transmission can be achieved, but power consumption increases and chip area is increased
Solution Approach 1:
The patent extracts the parameter passing function from external hardware components (port registers, dual-port RAM) and integrates it directly into the processor's instruction set architecture. By using a specialized instruction that directly writes to the slave processor's memory space through the instruction cache, the solution eliminates the need for separate Mailbox hardware, thereby reducing power consumption and chip area while maintaining reliable parameter transmission.
2Reliability
If a Mailbox mechanism using port registers or dual-port RAM is used to pass parameters between processors, then parameter transmission can be achieved, but chip area is increased
Solution Approach 1:
The patent removes the Mailbox hardware component (port registers or dual-port RAM) that occupies chip area and replaces it with a software-based solution using processor instructions. The master processor uses a special instruction to directly configure parameters in the slave processor's memory space through the instruction cache, eliminating the need for dedicated hardware and reducing chip area.
Solution Approach 2:
The patent merges the parameter passing function with the existing processor instruction set and memory architecture. By integrating the parameter transmission capability into the processor's internal structure (instruction cache, memory space), the solution combines multiple functions into a unified system, thereby reducing the need for separate hardware components and minimizing chip area.
3Reliability
If parameters are accessed through peripheral port registers, then parameter transmission is achieved, but cycle delay increases and parameter transmission efficiency is reduced
Solution Approach 1:
The patent extracts the parameter access operation from the peripheral port register interface and moves it directly into the processor's instruction execution path. By using a specialized instruction that directly writes to the slave processor's memory space through the instruction cache, the solution eliminates the peripheral access cycle delay, achieving faster parameter transmission without compromising reliability.
Data Source
AI summary
The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.