Programmable Processor Circuit for Data Word Parity Checking
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Solution Overview
Problem
In data processing equipment, the use of programmable processors for cumulative computations in communication streams leads to increased processor complexity and power consumption, especially when performing ancillary tasks like parity computations and error detection.
Innovation Solution
The implementation of processing circuitry that operates in bursts of programmable instructions during data reception, with suspended operations between bursts to minimize power consumption and reduce complexity, utilizing asynchronous timing and adaptable frequency adjustment based on input signal characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable processor is used to perform cumulative computations during data reception, then processing flexibility is improved, but processor complexity increases
Solution Approach 1:
The patent segments the processing operations into distinct bursts corresponding to each data word reception. The programmable processor executes a series of instructions for each data word, then enters a low-power suspended state until the next data word arrives. This segmentation allows the use of a simpler processor that operates intermittently rather than requiring a continuously operating complex processor.
Solution Approach 2:
The processor operates in periodic bursts synchronized with the arrival of data words. Between bursts, the processor suspends operation to reduce power consumption and complexity requirements. The periodic activation is triggered by detection of incoming data words, creating a rhythm of active processing followed by idle suspension that matches the communication stream characteristics.
2Reliability
If a programmable processor operates continuously to perform cumulative computations, then processing completeness is improved, but power consumption increases
Solution Approach 1:
The processor switches between active and suspended states periodically, activating only when a data word is detected and suspending operation between data word arrivals. This periodic operation maintains processing completeness for all incoming data while dramatically reducing average power consumption compared to continuous operation.
Solution Approach 2:
The system uses the incoming communication stream itself to trigger processor activation. The detection of a data word automatically initiates the processing burst, and completion of processing automatically triggers suspension. This self-triggering mechanism ensures no data is missed while eliminating the need for continuous monitoring, reducing power consumption.
3Measurement precision
If processing operations are performed quickly after all bits are received, then result accuracy is improved, but processing circuitry complexity increases
Solution Approach 1:
The patent performs preliminary cumulative processing during the reception of each bit, updating intermediate results as each bit arrives. This preliminary action allows the final computation to be completed quickly after all bits are received using simple finalization logic, rather than requiring complex circuitry to process all bits simultaneously at the end.
Solution Approach 2:
The computation is segmented into incremental updates during bit reception and a finalization step after reception completes. Each segment uses relatively simple processing, with the cumulative effect achieving high accuracy. This segmentation avoids the need for complex circuitry that would be required to perform all computations simultaneously.
Data Source
AI summary
A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.