Reconfigurable Processor Partitioning for Isolated Parallel Graph Execution

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Solution Overview

Problem

Existing reconfigurable processors face challenges in efficiently executing multiple, unrelated application graphs simultaneously due to complex distribution and loading procedures of configuration files, which are time-consuming and hinder parallel processing.

Innovation Solution

A reconfigurable data processor with a bus system and memory access controller that partitions configurable units into sets, enabling independent execution and configuration of application graphs, while confining memory access to allocated spaces, using virtual addresses and dynamic reconfiguration routines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If configuration files are distributed and loaded using existing procedures, then reconfigurable processors can execute application graphs, but the procedures are complex and time-consuming, preventing simultaneous execution of multiple application graphs

Engineering Contradiction:
Improveexecution speed of application graphsVSAvoidconfiguration file loading time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the reconfigurable processor into multiple isolated sets of configurable units, each capable of independently executing application graphs. This segmentation allows parallel configuration and execution of multiple application graphs simultaneously, eliminating the sequential bottleneck in configuration file loading and enabling concurrent productivity improvements.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple application graphs are executed simultaneously in a single reconfigurable processor, then processing throughput increases, but configuration management becomes complex and interference between applications may occur

Engineering Contradiction:
Improvethroughput of application graph executionVSAvoidconfiguration management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor is segmented into isolated sets of configurable units, with each set dedicated to a specific application graph. This physical segmentation simplifies configuration management by allowing independent configuration of each set without affecting others, reducing the complexity of managing multiple simultaneous applications while maintaining high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a configuration controller that acts as an intermediary to manage configuration files for multiple application graphs. The controller distributes and loads configuration files for different sets independently, simplifying the overall configuration management process while enabling simultaneous execution of multiple applications.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If configurable units are shared among multiple applications, then resource utilization is efficient, but applications may interfere with each other and require complex isolation mechanisms

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidisolation between application graphs
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The reconfigurable processor is divided into multiple isolated sets of configurable units, with each set dedicated to a specific application graph. This segmentation provides natural isolation between applications, ensuring that one application cannot interfere with another while maintaining efficient resource utilization within each set. The isolation is achieved through physical separation rather than complex software mechanisms.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250390456A1Partitioning for reconfigurable data processors
Publication Date: 2025.12.25 SAMBANOVA SYSTEMS INC
  • US20250390456A1 patent drawing
  • US20250390456A1 patent drawing
  • US20250390456A1 patent drawing

AI summary

A reconfigurable data processor comprises an array of configurable units and a bus system. The bus system includes a grid of switches connected to the array of configurable units. Each switch has a plurality of ports and a switch port disable register configurable to selectively disable one or more of the plurality of ports. A configuration controller is configured to load a configuration file that sets the switch port disable registers to partition the array into a plurality of isolated sets of configurable units. Each set is blocked from communicating with configurable units outside the set via the bus system.