Processor Performance State Security Logic

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Solution Overview

Problem

Current computing systems face security vulnerabilities during performance state changes of processors, as unauthorized access can lead to improper operating voltage and frequency changes, potentially causing security breaches.

Innovation Solution

Implementing performance state security logic that adjusts operating level tolerance ranges during state changes, allowing for secure monitoring and control by separating voltage and frequency changes as discrete operations, thereby reducing the likelihood of security breaches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If performance state changes are implemented to optimize processor operation, then processing performance is improved, but security vulnerabilities increase due to unauthorized access during state transitions

Engineering Contradiction:
Improveprocessing performanceVSAvoidsecurity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A security logic component is introduced as an intermediary between the performance state control logic and the processor cores. This security logic monitors and validates performance state change requests, adjusting operating level tolerance ranges during transitions to prevent unauthorized access while maintaining legitimate performance optimizations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If operating level tolerance ranges are adjusted during state transitions, then security is improved by preventing unauthorized access, but the complexity of monitoring and control increases

Engineering Contradiction:
ImprovesecurityVSAvoidmonitoring and control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The security monitoring function is segmented into discrete components: performance state control logic handles state transitions, security logic handles monitoring and validation, and voltage/clock regulators handle actual hardware control. This segmentation allows each component to focus on specific tasks, reducing overall system complexity while maintaining comprehensive security.

Inventive Principle:
Principle #1Segmentation

3Reliability

If voltage and frequency changes are separated as discrete operations, then security is improved by reducing exposure time during transitions, but the time required for state changes increases

Engineering Contradiction:
ImprovesecurityVSAvoidstate change time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The performance state change process is segmented into separate voltage change and frequency change operations. The security logic monitors each operation independently, adjusting tolerance ranges only when needed. This segmentation allows for more precise security control while minimizing the time window for potential unauthorized access.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10146282B2System and method for monitoring and controlling a performance state change
Publication Date: 2018.12.04 ADVANCED MEDICAL DEVICES
  • US10146282B2 patent drawing
  • US10146282B2 patent drawing
  • US10146282B2 patent drawing

AI summary

The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request. The system further includes performance state security logic operative to adjust, in response to the request, an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state.