Processor Peripheral Unit Down-Counter Synchronization
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Solution Overview
Problem
Traditional computing designs face challenges in achieving reliable and fast communication and control between processors and peripherals, with standalone timers requiring significant overhead and expensive FPGA solutions for high-resolution peripheral emulation.
Innovation Solution
A processor arrangement with a core processor and a peripheral unit connected by input/output unit lines, utilizing two down-counters to generate events for synchronizing signaling and communication, allowing cycle-correct interaction with external peripherals and reducing core processor load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standalone timers are used for peripheral control, then timing precision is improved, but device complexity and overhead increase
Solution Approach 1:
The patent combines the timer functionality with the peripheral control unit by integrating two down-counters directly into the peripheral unit that controls input/output lines. This merging eliminates the need for separate standalone timers, reducing device complexity while maintaining precise timing control through the integrated counters that generate events for synchronizing peripheral operations.
2Measurement precision
If high-resolution peripheral emulation is implemented, then communication precision is improved, but cost and device complexity increase
Solution Approach 1:
The peripheral unit is designed with multi-functionality, serving both as a control unit for input/output lines and as a high-resolution timer/counter. The two down-counters can operate in different modes (independent or combined) to provide various timing resolutions, allowing the same hardware to emulate different peripheral functions with high precision without requiring separate dedicated circuits for each function.
3Reliability
If cycle-correct interaction is achieved, then reliability is improved, but processing overhead increases
Solution Approach 1:
The down-counters operate autonomously to generate timing events without requiring continuous processor intervention. Once configured, the counters automatically decrement and generate events when reaching zero, enabling the peripheral unit to self-manage timing-critical operations. This self-service mechanism ensures cycle-correct interaction for reliable communication while minimizing the processing overhead on the core processor.
Data Source
AI summary
According to an aspect, there is provided a solution for controlling communication in a processor arrangement, the arrangement comprising a core processor, a peripheral unit operationally connected to the core processor; a given number of input/output unit lines, the arrangement being further connectable to external peripherals. The solution comprises performing down-counting (600) utilising at least one counter of two down-counters of a given length, generating (602) an event when a counter reaches zero value and synchronizing (604) signalling on input/output unit lines and communication of core processor with external peripherals on the basis of the event.