Processor Peripheral Segmentation for Bidirectional Communication
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Solution Overview
Problem
Existing processors face challenges in efficiently managing bidirectional communication schemes with external devices, such as sensors, due to the need for constant switching between transmitting and receiving data, which diverts significant processing resources and limits the processor's ability to perform other tasks.
Innovation Solution
The integration of peripherals like a timer peripheral, a direct memory access (DMA) controller, and a buffer circuit in processors allows for automated data sampling with reporting devices configured for bidirectional communication. This setup includes a buffer circuit between the processor's data line and the reporting device, enabling the processor's core to focus on other tasks while peripherals handle communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor uses bit banging to manually clock out and capture bits for bidirectional communication, then communication with the external device is maintained, but the processor core is occupied and cannot perform other critical tasks
Solution Approach 1:
The processor is segmented into a core and separate peripheral units (USART, SPI, I2C). The peripheral units handle bidirectional communication independently from the core, allowing the core to execute other tasks while communication functions are performed by dedicated hardware modules that do not block core operations.
Solution Approach 2:
Peripheral units act as intermediaries between the processor core and external communication devices. These intermediary components manage the bidirectional communication protocol, timing signals, and data transfer, freeing the core from direct involvement in communication overhead while ensuring reliable data exchange.
2Reliability
If the processor dedicates core resources to bidirectional communication switching, then communication compliance is ensured, but the processor cannot simultaneously perform wireless communication and other critical tasks
Solution Approach 1:
The processor architecture is divided into an independent core and specialized peripheral communication units. Each peripheral (USART, SPI, I2C) is self-contained and handles specific communication protocols, allowing the core to be allocated to multiple different tasks including wireless communication without compromising communication compliance.
Solution Approach 2:
The processor core is designed with multi-functionality to perform various tasks including wireless communication, sensor data processing, and control functions. By offloading communication-specific functions to dedicated peripherals, the core becomes a universal resource that can be dynamically allocated to different critical tasks based on system needs.
3Measurement precision
If the processor actively manages timing signals and data sampling for bidirectional communication, then communication accuracy is maintained, but processing resources are consumed and response time for other tasks increases
Solution Approach 1:
Peripheral communication units are equipped with built-in timing mechanisms and control logic that automatically generate timing signals, manage data sampling intervals, and control bidirectional communication sequences. This self-service capability ensures precise data sampling and timing without requiring continuous core intervention, thereby minimizing processor workload and maximizing response time for other tasks.
Data Source
AI summary
A control device may include a processor may include a core, a timer peripheral, and a peripheral direct memory access controller. The processor may include a receive port coupled to a communication port of the reporting device via a communication line. The control device may include a timer peripheral that can generate an enable signal and a timing signal, and a buffer circuit that may include an enable port for the enable signal for enabling/disabling the buffer circuit, an input port for the timing signal, and an output port coupled to the communication line. The processor may enable/disable the buffer circuit to control the timing of data bit(s) transmission across the communication line by the reporting device. The peripheral direct memory access controller may store the data bit(s) in a receive buffer during the bit period, and the core may subsequently retrieve the data bit(s) from the receiver buffer.