Multithreaded Processor Pick Unit Divider Resource Scheduling

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Solution Overview

Problem

Multithreaded processors face challenges in efficiently managing divider resources among multiple threads, leading to potential bottlenecks and reduced throughput due to the need for concurrent execution of divide operations.

Innovation Solution

A multithreaded processor architecture that includes a pick unit to select and prioritize divide instructions, transitioning threads to a wait state until previous divide instructions complete, and utilizing a divider queue to temporarily store instructions, allowing for the execution of multiple divide operations without stalling other threads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple threads execute divide operations concurrently in a multithreaded processor, then thread processing throughput is improved, but resource conflicts and bottlenecks occur due to limited divider resources

Engineering Contradiction:
Improvethread processing throughputVSAvoidresource conflict management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processor segments thread execution into distinct states (ready state and wait state) and uses a pick unit to selectively choose which threads access the divider resource in each cycle. This segmentation allows multiple threads to be managed concurrently while preventing resource conflicts by ensuring only one thread executes divide operations at a time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pick unit performs preliminary selection of threads that will access the divider resource before execution begins. By pre-selecting threads in the ready state and transitioning them to the wait state after selection, the system prepares the execution schedule in advance, avoiding conflicts and ensuring smooth concurrent processing of multiple threads.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If a single divider resource is shared among multiple threads, then device complexity is reduced, but execution speed decreases due to sequential processing requirements

Engineering Contradiction:
Improvedivider resource structureVSAvoiddivide operation execution speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The processor maintains continuous useful action by keeping multiple threads in the ready state with divide instructions prepared for execution. When one thread completes its divide operation, another thread from the ready state is immediately selected by the pick unit and transitioned to execution, ensuring the divider resource is continuously utilized without idle cycles and maintaining high execution speed.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If threads are stalled waiting for divider availability, then resource conflicts are avoided, but loss of time increases due to thread idle periods

Engineering Contradiction:
Improveresource conflict avoidanceVSAvoidthread wait time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically transitions threads between ready state and wait state based on divider availability. The pick unit continuously monitors which threads are ready and which have completed execution, dynamically adjusting which threads access the divider resource. This dynamic state management ensures threads only wait when absolutely necessary while maximizing overall processor utilization and minimizing total wait time across all threads.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7941642B1Method for selecting between divide instructions associated with respective threads in a multi-threaded processor
Publication Date: 2011.05.10 ORACLE AMERICAN INC
  • US7941642B1 patent drawing
  • US7941642B1 patent drawing
  • US7941642B1 patent drawing

AI summary

In one embodiment, a multithreaded processor includes a multithreaded instruction source that may provide a plurality of instructions each corresponding to a respective one of a plurality of threads. The multithreaded processor also includes a pick unit coupled to the multithreaded instruction source. The pick unit may select in a given cycle, a first divide instruction corresponding to one thread of the plurality of threads and a second divide instruction corresponding to another thread of the plurality of threads based upon a thread selection algorithm. Further, the multithreaded processor includes a storage coupled to a functional unit including a divider configured to execute the first divide instruction and the second divide instruction. The storage may store one of the first and the second divide instructions during execution of the other of the first and the second divide instructions.