Processor Offloading to PIM Devices via Fixed Function Operations
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Solution Overview
Problem
Current Processing-in-Memory (PIM) architectures face complexity and overhead in offloading instructions due to requirements for changes in the threading model, dedicated hardware, and atomicity enforcement, which complicates the transition between CPU and PIM threads and increases power consumption.
Innovation Solution
The implementation of a hardware and instruction set architecture that supports offloading computations to PIM devices or accelerators with fixed function capability, allowing cacheable, coherent data to be processed without software cache management, and enabling instructions to be offloaded without launching additional threads or modifying the threading model.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are offloaded to PIM devices with changes in threading model and dedicated hardware, then processing capability is improved, but device complexity and overhead increase
Solution Approach 1:
The processor core is designed to execute both traditional instructions and offload instructions without requiring dedicated PIM-specific hardware threads. The same core resources (instruction fetch, decode, register file) are used for both CPU and PIM instruction execution, making the processor universal and eliminating the need for separate threading infrastructure.
Solution Approach 2:
The offload instruction mechanism extracts the complexity of PIM thread management from the processor core by using a simple instruction format that directly specifies PIM device identifiers and memory addresses, removing the need for complex thread scheduling and context switching hardware that would otherwise be required.
2Reliability
If atomicity enforcement is implemented for PIM thread transitions, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The system achieves atomicity self-service through the natural ordering guarantees of the memory interface and the sequential execution model of the processor core. Offload instructions are executed in program order within the core, and memory operations to the PIM device inherit this ordering, eliminating the need for additional atomicity enforcement hardware and associated power consumption.
3Productivity
If data is frequently fetched from memory due to low temporal reuse, then processing continues, but energy efficiency deteriorates
Solution Approach 1:
The PIM device acts as an intermediary between main memory and the processor core, performing computational operations directly on data stored in memory or in intermediate buffers within the PIM device. This eliminates the need to frequently fetch data to the core for processing, as the PIM device can operate on cached or buffered data locally, significantly reducing memory traffic and improving energy efficiency.
Data Source
AI summary
Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.