Processor Architecture Resolving Pipeline Dependencies Without NOPs

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Solution Overview

Problem

Traditional processor architectures face challenges in managing instruction dependencies and pipeline hazards, often requiring the insertion of No Operation (NOP) instructions to avoid hazards, which wastes memory resources and complicates compiler development.

Innovation Solution

A processor architecture that evaluates operand and execution dependencies, holds instructions until resources are available, and dispatches them for execution only when all dependencies are resolved, eliminating the need for NOPs and enabling parallel execution and speculative execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If NOP instructions are inserted into the instruction code to resolve pipeline hazards, then execution dependencies are avoided, but instruction memory resources are wasted

Engineering Contradiction:
Improvepipeline hazard resolutionVSAvoidinstruction memory resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts and removes NOP instructions from the instruction code stream before execution. The instruction filter detects NOPs and eliminates them, allowing the processor to execute only meaningful instructions. This resolves pipeline hazards without consuming instruction memory resources for no-operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an instruction filter as an intermediary component between the instruction memory and the execution unit. This filter analyzes incoming instructions, identifies NOPs, and selectively blocks them from reaching the execution pipeline. The intermediary resolves dependencies without requiring NOPs to be stored in memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If NOP instructions are used to resolve execution pipeline dependencies, then pipeline hazards are avoided, but compiler development is complicated

Engineering Contradiction:
Improvepipeline hazard resolutionVSAvoidcompiler development
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements self-service by enabling the processor hardware itself to automatically detect and filter NOP instructions without compiler intervention. The instruction filter operates autonomously to identify and remove NOPs from the execution stream, freeing compilers from the burden of manually inserting dependency-resolution instructions.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The instruction filter extracts NOP instructions from the code stream at runtime, eliminating the need for compilers to embed special NOP sequences for dependency management. This separation of concerns simplifies compiler development while maintaining reliable pipeline execution.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If the processor waits for resource availability before executing instructions, then dependency resolution is achieved, but execution speed may be reduced

Engineering Contradiction:
Improvedependency resolutionVSAvoidinstruction execution speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by pre-filtering NOP instructions from the instruction stream before they enter the execution pipeline. By removing unnecessary instructions in advance, the processor avoids wasting cycles executing no-operations and can maintain higher execution speed while still resolving dependencies through the filter mechanism.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11275590B2Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory
Publication Date: 2022.03.15 HUAWEI TECH CO LTD
  • US11275590B2 patent drawing
  • US11275590B2 patent drawing
  • US11275590B2 patent drawing

AI summary

Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.