Processor Hardware Pipeline Register Bank Configuration
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Solution Overview
Problem
Constructing a task descriptor and writing it to the register bank in processors with dedicated hardware pipelines results in idle time as the hardware waits for the software to set up the next task, leading to inefficiencies in task processing.
Innovation Solution
Implementing a processor with multiple buffered configuration registers and control circuitry that allows the hardware pipeline to start processing the next task while the software is setting up or post-processing the current task, using selectors to manage register sets and flags to ensure seamless task handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the hardware pipeline waits for software to write the task descriptor to the register bank, then the software can properly configure the task parameters, but the hardware pipeline experiences idle time waiting for the descriptor
Solution Approach 1:
The patent applies preliminary action by allowing software to write task descriptors to the register bank in advance, before the hardware pipeline is ready to process them. The descriptor writing operation is decoupled from the hardware processing timing, enabling software to prepare task configurations ahead of time without causing hardware idle waits. The hardware pipeline can then immediately process descriptors that are already available in the register bank.
Solution Approach 2:
The register bank serves as an intermediary buffer between software and hardware pipeline. Software writes descriptors to the register bank independently of hardware readiness, and the hardware pipeline reads descriptors from the register bank when ready. This intermediary structure decouples the software-hardware synchronization, eliminating the idle time caused by direct waiting while ensuring proper task configuration.
2Productivity
If the software writes the task descriptor to the register bank before the hardware pipeline is ready, then the hardware can start processing immediately, but the software and hardware operation timing becomes unsynchronized
Solution Approach 1:
The patent segments the task submission process into independent software writing operations and hardware reading operations. Software writes descriptors to specific register locations without needing to coordinate with hardware readiness, while hardware reads from these registers when ready. This segmentation eliminates complex synchronization requirements while maintaining high throughput, as each operation can proceed independently at its own pace.
Solution Approach 2:
The hardware pipeline performs self-service by autonomously reading task descriptors from the register bank when it is ready to process, without requiring software intervention or synchronization signals. Similarly, software independently writes descriptors to the register bank without needing to know when hardware is ready. This self-service approach simplifies the interface between software and hardware while maximizing productivity.
Data Source
AI summary
A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.