Processor Pipeline Switching for Thread and Register Conflicts
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Solution Overview
Problem
Existing processors face inefficiencies in pipeline execution due to conflicts such as resource, data, and control correlations, particularly with limited general-purpose registers, which restrict instruction level parallelism and hardware resource utilization.
Innovation Solution
A processor architecture that switches between different instruction execution modes, supporting varying numbers of threads and general-purpose register sets, using register renaming techniques to manage conflicts and optimize resource utilization through a switching unit that adjusts pipeline architecture based on selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a processor uses a fixed pipeline architecture with limited general-purpose registers, then the device complexity is reduced, but the instruction level parallelism and resource utilization deteriorate
Solution Approach 1:
The patent implements dynamic pipeline architecture switching between different execution modes (single-threaded and multi-threaded) based on workload requirements. The processor can transition between a simplified pipeline configuration for single-threaded execution and an expanded configuration with additional rename registers and pipeline stages for multi-threaded execution, allowing the system to adapt its complexity to match the actual computational demands
Solution Approach 2:
The processor design incorporates a universal pipeline architecture that can function in multiple execution modes. The same physical hardware resources (registers, pipeline stages, execution units) can be allocated differently depending on whether the processor is executing single-threaded or multi-threaded workloads, maximizing resource utilization across different operational scenarios
2Adaptability or versatility
If a processor supports N threads with a first general-purpose register set, then the adaptability to multi-threaded workloads is improved, but the register resources available per thread are reduced
Solution Approach 1:
The patent introduces rename registers as intermediary storage elements that decouple the logical thread view from physical register allocation. These rename registers act as a buffer layer between the thread execution logic and the actual register file, allowing multiple threads to share physical registers while maintaining independent logical register states through renaming and allocation mechanisms
Solution Approach 2:
The processor dynamically changes the register allocation parameters based on the number of active threads. When switching between single-threaded and multi-threaded modes, the system adjusts the number of available rename registers, the register file organization, and the allocation strategy to optimize the balance between thread count and register resources per thread
3Adaptability or versatility
If a processor switches between different instruction execution modes with varying thread support, then the adaptability to diverse workloads is improved, but the device complexity increases
Solution Approach 1:
The processor implements dynamic mode switching capability that allows transition between single-threaded and multi-threaded execution modes based on workload characteristics. This dynamic adaptation enables the system to optimize performance for different workload types while managing complexity through controlled configuration changes rather than supporting all modes simultaneously with full hardware duplication
Data Source
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Figure 1B
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AI summary
An instruction execution method, a processor and an electronic apparatus. The instruction execution method comprises: according to a selection signal, switching the pipeline structure of a processor between a first instruction execution mode and a second instruction execution mode, wherein the first instruction execution mode supports N threads and is suitable for a first general-purpose register set of an instruction set; the second instruction execution mode supports M threads and is suitable for a second general-purpose register set of the instruction set; the first general-purpose register set is less than the second general-purpose register set; M and N are positive integers; and N is greater than M.