Processor Pipeline Handling Wait Instructions
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Solution Overview
Problem
Conventional pipeline processing is inefficient when handling WAIT instructions, as it leads to temporary suspension of computation and re-fetching of instructions, resulting in time loss and slowed processing speed due to the need for pipeline flushing and re-execution.
Innovation Solution
A processor and pipeline processing method that includes a fetch unit, decoding unit, computation execution unit, instruction holding unit, and execution target thread selection unit, which hold instruction fetch information for the next instruction after a WAIT instruction and resume processing from the decoding stage upon cancellation of the wait state, eliminating the need for re-fetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pipeline flushing is performed when WAIT instruction is executed, then correct instruction execution order is maintained, but processing speed deteriorates due to re-fetching instructions
Solution Approach 1:
The patent applies preliminary action by storing the address of the instruction following the WAIT instruction in advance (in the pipeline flush address storage unit) before the pipeline flush occurs. When the WAIT instruction is detected, the system immediately retrieves the pre-stored address to resume execution after the wait condition is satisfied, eliminating the need to re-fetch instructions and thereby maintaining processing speed while ensuring correct execution order.
2Reliability
If pipeline processing is suspended for WAIT instruction, then wait condition can be properly handled, but productivity decreases due to temporary stop of computation
Solution Approach 1:
The patent maintains continuity of useful action by allowing other threads to continue executing instructions in the pipeline while one thread is waiting. The execution target determination unit can switch to another thread that does not have a pending WAIT condition, ensuring that the pipeline remains productive and computation continues without complete suspension, thereby maintaining high productivity while properly handling wait conditions.
3Reliability
If instruction re-fetching is performed after WAIT instruction, then pipeline is refreshed, but time loss occurs due to re-execution of fetch and decode operations
Solution Approach 1:
The patent applies preliminary action by pre-storing the address of the instruction following the WAIT instruction in the pipeline flush address storage unit before the wait condition is resolved. When the WAIT instruction is detected, the system immediately retrieves the pre-stored address to resume execution, eliminating the time-consuming re-fetch and re-decode operations and thereby minimizing time loss while maintaining pipeline reliability.
Data Source
AI summary
A pipeline processing unit includes a fetch unit that fetches the instruction for the thread having an execution right, a decoding unit that decodes the instruction fetched by the fetch unit, and a computation execution unit that executes the instruction decoded by the decoding unit. When the WAIT instruction for the thread having the execution right is executed, an instruction holding unit holds instruction fetch information on a processing target instruction to be processed immediately after the WAIT instruction. An execution target thread selection unit selects a thread to be executed based on a wait command and, in response to a wait state started from the execution of the WAIT instruction being canceled, processes the processing target instruction from decoding thereof based on the instruction fetch information on the processing target instruction held in the instruction holding unit.