Processor Port Control via Timer-Counter Pulse Generation

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Solution Overview

Problem

In electronic circuitry, particularly in processors, the setting and clearing of ports can take an indeterminate amount of time due to asynchronous bus masters, such as DMA engines, making it challenging to control ports for a defined or desired period under software control.

Innovation Solution

A method and apparatus that utilize a processor to execute instructions for port control by writing a value to a storage location and initializing a count operation with a timer, ensuring that the value is provided to the port only when the final count value is reached, allowing for precise control and generation of pulses for a desired period.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If asynchronous bus masters (such as DMA engines) are used for data transfer, then data transfer efficiency is improved, but port control timing becomes indeterminate and difficult to control for a defined period

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidport control timing precision
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system pre-configures the port control mechanism by setting up a timer/counter unit and loading the desired pulse duration value before the actual port toggling operation. This preliminary setup ensures that when the port control instruction is executed, the timing is already predetermined and will execute precisely without being affected by asynchronous bus operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A timer/counter unit is introduced as an intermediary component between the processor and the port. This mediator receives the desired pulse duration from the processor, counts the clock cycles independently, and controls the port toggling based on its own timing sequence, thereby isolating the port control timing from the asynchronous bus operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If software control is implemented for port toggling, then flexibility in controlling port duration is improved, but the control mechanism becomes more complex and requires additional circuitry

Engineering Contradiction:
Improveport control flexibilityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The timer/counter unit is designed to serve multiple functions: it can measure time delays, generate pulse widths, and control port toggling sequences. By making this single component multi-functional, the system achieves flexible software-controlled port timing without requiring separate dedicated circuitry for each function, thereby reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The timer/counter unit operates autonomously once initialized. It automatically counts clock cycles and generates the appropriate control signals for port toggling without requiring continuous processor intervention. This self-service capability reduces the burden on the processor and simplifies the control mechanism while maintaining full software programmability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8914564B2Port control apparatus and associated methods
Publication Date: 2014.12.16 SILICON LABORATORIES INC
  • US8914564B2 patent drawing
  • US8914564B2 patent drawing
  • US8914564B2 patent drawing

AI summary

A method of controlling a port in an apparatus includes receiving an instruction for execution by a processor. The method further includes executing the instruction, by writing a value to a storage location corresponding to the port, and by initializing a count operation. The method further includes proceeding with the count operation until a final count value is reached, and providing to the port the value written to the storage location.