Processor Power Limiter With Multi-Timescale Budget Allocation
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Solution Overview
Problem
Processor-based systems face challenges in managing power consumption and thermal limits, particularly in systems-on-a-chip (SoCs) with multiple processors, leading to potential violations of shorter duration power limits and adverse effects on performance and battery life.
Innovation Solution
A power limiter circuit allocates power budgets based on multiple time-based power limits, dynamically managing power consumption to optimize performance and adhere to thermal and skin temperature limits by comparing current consumption with various time-scaled limits to generate optimized power limit budgets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor executes workloads at higher performance levels, then the processing speed and computational capability are improved, but the power demand exceeds the available power from the battery
Solution Approach 1:
The power limiter circuit dynamically adjusts power allocation to different subsystems based on real-time power consumption monitoring and multiple time-based power limits. The circuit continuously monitors power consumption and adjusts power delivery to processing units and other subsystems to maintain optimal performance while staying within power constraints, enabling the system to adaptively balance processing speed and power consumption.
2Productivity
If multiple processors execute workloads concurrently, then the overall computational throughput is improved, but the power consumption increases and may violate power limits
Solution Approach 1:
The power limiter circuit segments the total power budget into separate power limits for different subsystems, including first power limits for processing units and second power limits for other subsystems. This segmentation allows concurrent operation of multiple processors by allocating appropriate power shares to each, enabling them to execute workloads simultaneously while the overall system remains within power constraints through coordinated power management.
3Use of energy by moving object
If the system operates without considering shorter duration power limits, then the average power consumption may be within limits, but the shorter duration power limits are violated affecting performance
Solution Approach 1:
The power limiter circuit is configured to proactively enforce multiple time-based power limits before violations occur. It monitors power consumption across different time windows and adjusts power delivery in advance to prevent exceeding any power limits, including shorter duration limits. This preliminary action ensures both average power consumption and peak power demands remain within specified limits, maintaining reliability and performance.
4Productivity
If thermal and skin temperature limits are not considered, then power consumption can be maximized for performance, but temperature limits are exceeded causing performance degradation
Solution Approach 1:
The power limiter circuit incorporates feedback mechanisms that monitor temperature and power consumption, adjusting power delivery to processing units based on thermal conditions. When temperature approaches thermal or skin limits, the circuit reduces power allocation to prevent overheating, ensuring the system operates within safe temperature ranges while maximizing performance within those constraints.
Data Source
AI summary
Power limiting in a processor-based system based on allocating power budgets for different sub-systems based on multiple time-based power limits is disclosed. The processor-based system has multiple power consuming sub-systems (e.g., non-processing unit (PU) and PU sub-systems) that demand and consume power from a power source of the processor-based system. To limit overall power consumption of the processor-based system over different time-based power limits, the processor-based system includes a power limiter circuit. The power limiter circuit is configured to manage multiple, different time-based (e.g., time constant) power limits for the processor-based system and to allocate corresponding power limit budgets to constrain power consumption of different sub-systems based on the multiple time-based power limits. The power limiter circuit can be configured to constrain power consumption of a PU sub-system to a total PU sub-system power limit budget based on the multiple time-based power limits.