Processor Power Control via Dynamic Thread Load Balancing

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Solution Overview

Problem

In distributed computing systems, existing power management strategies fail to ensure uniform performance across multiple processors, leading to non-deterministic performance variations and complications in debugging applications, as each processor manages its power autonomously without considering others, resulting in uneven completion times of parallel threads.

Innovation Solution

A system with a power control unit and communication fabric that allows dynamic load balancing by associating each thread with a resource monitor and a class of service, using machine-specific registers to manage power and performance across processor cores, enabling dynamic frequency adjustments and power allocation based on thread priority without interrupting processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If each processor manages its power autonomously without considering other processors, then power management simplicity is improved, but performance uniformity across processors deteriorates

Engineering Contradiction:

Improvepower management simplicityVSAvoidperformance uniformity

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent introduces a central power management entity (power management circuit or hypervisor) that acts as an intermediary between processors and power management functions. This intermediary collects performance data from all processors, makes centralized power management decisions, and distributes power allocation to individual processors, thereby achieving both centralized control for uniformity and autonomous operation simplicity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback mechanisms where processors report their performance metrics and power consumption to the central power management entity, which then adjusts power allocation based on this feedback. This closed-loop control ensures that power distribution adapts to actual system conditions while maintaining performance uniformity across processors.

Inventive Principle:

Principle #23Feedback

2Device complexity

If processors operate autonomously with independent power management, then system complexity is reduced, but parallel thread completion uniformity deteriorates

Engineering Contradiction:

Improvesystem complexityVSAvoidthread completion time variation

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The central power management entity serves as an intermediary that coordinates power allocation across all processors, ensuring that parallel threads receive appropriate power resources to complete uniformly. This mediation reduces thread completion time variation without requiring complex inter-processor communication protocols.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements dynamic power allocation where the central power management entity continuously adjusts power distribution to processors based on real-time workload conditions. This dynamic adjustment ensures that parallel threads complete at similar times by adapting power resources to match actual processing needs, reducing completion time variation.

Inventive Principle:

Principle #15Dynamics

3Speed

If power management software reacts slowly to create fine-grained power policy, then response speed is improved, but performance variation among processors increases

Engineering Contradiction:

Improvepower policy response speedVSAvoidperformance variation

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent segments power management into two layers: a fast local layer where processors can make immediate power adjustments based on local conditions, and a slower central layer for fine-grained policy decisions. This segmentation enables both fast response to urgent conditions and precise control for performance uniformity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements continuous power monitoring and adjustment mechanisms that operate at different time scales. Fast local adjustments maintain continuous response to immediate workload changes, while slower central policy updates provide fine-grained control, ensuring both rapid response and performance consistency without interruption.

Inventive Principle:

Principle #20Continuity of useful action

4Adaptability or versatility

If processor performance varies in large distributed computing systems, then adaptability to different workloads is improved, but debugging complexity increases due to non-determinism

Engineering Contradiction:

Improveworkload adaptabilityVSAvoiddebugging complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates equipotential performance conditions across processors by implementing centralized power management that equalizes power allocation and performance characteristics. This establishes a deterministic baseline where all processors operate under comparable conditions, eliminating non-determinism and simplifying debugging while maintaining adaptability through controlled power adjustment.

Inventive Principle:

Principle #12Equipotentiality

Data Source

PatentUS10146287B2Processor power monitoring and control with dynamic load balancing

Publication Date: 2018.12.04 INTEL CORP

AI summary

Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.