Processor Performance Power Control via Roofline Model Analysis
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Solution Overview
Problem
Existing methods for power saving control in processors, such as those described in Patent Documents 1 and 2, fail to provide accurate performance control adapted to arithmetic application algorithms, leading to delayed power saving and insufficient control over multi-core configurations and main storage apparatus frequencies.
Innovation Solution
The proposed information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. This system acquires computational strength data for each execution block and uses a roofline model to control the operation frequency and number of cores of the processor, as well as the operation frequency of the main storage apparatus, to perform performance power control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If statistical information regarding memory access is used inside a processor for power saving control, then power consumption is reduced, but power performance control with high accuracy adapted to arithmetic application algorithms cannot be performed
Solution Approach 1:
The patent pre-calculates and stores computational strength data for each execution block in advance, before actual execution. This preliminary action enables the power control unit to make accurate power performance control decisions without delay, as the computational strength information is already available when needed for control decisions.
Solution Approach 2:
The patent introduces computational strength data as an intermediary metric that bridges the gap between simple load monitoring and accurate algorithm-specific performance prediction. This intermediary data, derived from roofline model analysis, enables precise power control adapted to arithmetic application algorithms while maintaining low computational overhead.
2Use of energy by moving object
If computational strength data is not used in power saving control, then power consumption is reduced, but power saving control is delayed and processor frequency remains low particularly when high arithmetic performance is required
Solution Approach 1:
The patent performs preliminary calculation of computational strength data for each execution block before execution begins. This advance preparation ensures that when execution starts, the power control unit immediately has accurate information to make optimal frequency decisions, preventing any delay in power saving control and avoiding unnecessary low frequency states.
3Device complexity
If only operation frequency and command issue width control is performed, then device complexity is reduced, but sufficient power saving control cannot be performed
Solution Approach 1:
The patent segments power control into distinct levels: processor-level control (operation frequency and command issue width) and system-level control (main storage apparatus operation frequency). This segmentation allows comprehensive power saving while keeping each control module relatively simple, with the power control unit coordinating both levels based on computational strength data.
Solution Approach 2:
The patent makes the power control unit multi-functional by enabling it to control both processor parameters (operation frequency, command issue width) and main storage apparatus operation frequency. This universal control capability achieves sufficient power saving across the entire system without proportionally increasing device complexity.
Data Source
AI summary
An information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. The execution block computational strength data area holds computational strength data of each execution block constituting an arithmetic application that operates in a computer system including a processor and a main storage apparatus. The roofline model data storage unit holds a roofline model corresponding to an operation frequency and the number of cores of the processor, and an operation frequency of the main storage apparatus. The computational strength data acquisition unit acquires computational strength data of each execution block. The performance power control unit controls an operation frequency and the number of cores of the processor and an operation frequency of the main storage apparatus based on the roofline model and the computational strength data of each execution block.