Processor Power Control Unit Residency Time Measurement
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Solution Overview
Problem
Current techniques for determining the power state of non-CPU domains in integrated circuits rely on estimates, leading to suboptimal power management and missed energy-saving opportunities due to inaccuracies in residency time calculations.
Innovation Solution
Implementing a processor with a power control unit, interrupt generation unit, and timers to accurately measure the residency time of non-core domains, such as the graphics processing unit, allowing for the determination of an optimal power state based on actual residency times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If estimated residency times of non-core domains are used to determine power state, then device complexity is reduced, but measurement precision deteriorates leading to suboptimal power management
Solution Approach 1:
The patent introduces an intermediary measurement mechanism where the power control unit acts as a mediator between the non-core domain activity and the power state determination. This intermediary captures actual residency time data through interrupt signals and timer measurements, providing accurate input for power state decisions without requiring complex manual estimation processes.
Solution Approach 2:
The system implements feedback by continuously monitoring actual residency times of non-core domains and using this information to dynamically adjust power state decisions. The measured residency time data feeds back into the power control unit, enabling iterative optimization of power management based on real usage patterns rather than static estimates.
2Measurement precision
If actual residency time measurement is implemented, then measurement precision improves for power state determination, but device complexity increases due to additional hardware components
Solution Approach 1:
The power control unit is designed with multi-functionality, serving both as a power management controller and as a residency time measurement device. The interrupt generation unit and timer resources are shared between power state management and residency time measurement functions, reducing the need for dedicated separate components and minimizing overall device complexity.
Solution Approach 2:
The system implements self-service by having the power control unit automatically perform residency time measurements and power state determinations without requiring external intervention. The non-core domains self-report their activity status through interrupt signals, and the timer automatically captures residency time data, eliminating the need for complex external measurement infrastructure.
3Ease of operation
If power state is determined based on estimated residency times, then ease of operation is maintained, but energy conservation deteriorates due to missed power-saving opportunities
Solution Approach 1:
The system performs preliminary action by pre-configuring the timer and interrupt mechanisms to automatically capture residency time data before power state decisions are made. This preliminary measurement setup ensures that accurate residency time information is readily available when power state determination is needed, enabling immediate and accurate power-saving actions without operational delay.
Solution Approach 2:
The feedback mechanism continuously provides actual residency time information to the power control unit, enabling real-time optimization of power states. This feedback loop ensures that power-saving opportunities are captured based on actual usage patterns rather than estimates, maximizing energy conservation while maintaining automatic operation.
Data Source
AI summary
A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.