Processor Power Controller Using Package and Thread Hints
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Solution Overview
Problem
The increasing power requirements and energy consumption of multicore processors pose a significant challenge for energy efficiency, particularly in computing systems where existing power management techniques often rely on a single source of performance state hints, leading to complexity and inefficiency.
Innovation Solution
A power controller that utilizes both thread-level and package-level performance state hints to determine appropriate performance states for processor cores, allowing for flexible and independent control of voltage and frequency across multiple cores, enabling better power management and performance tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single source of performance state hints is used for power management, then the control logic is simpler, but the power management efficiency and adaptability deteriorate
Solution Approach 1:
The patent segments the performance state hint sources into two independent levels: package-level hints that apply to the entire processor package, and thread-level hints that apply to individual threads. This segmentation allows each level to provide guidance independently, improving power management adaptability without creating complex integration logic, as the hints are processed in a hierarchical manner where thread-level hints can override package-level hints when more specific information is available.
Solution Approach 2:
The patent introduces a new dimension to performance state control by adding thread-level granularity to the traditional package-level control. This creates a two-dimensional hint system where both package-wide and thread-specific performance states can be specified independently, enabling more precise power management without proportionally increasing control logic complexity.
2Measurement precision
If thread-level performance state control is implemented, then the power management precision is improved, but the device complexity increases
Solution Approach 1:
The patent segments performance state control into package-level and thread-level independent control mechanisms. Each level has its own hint registers and control logic, allowing precise thread-level power management without requiring complete redesign of the entire control system. The segmented approach enables incremental complexity addition while maintaining precision benefits.
Solution Approach 2:
The patent designs the performance state hint mechanism to serve multiple functions: package-level hints provide coarse-grained power management for the entire processor, while thread-level hints provide fine-grained control for individual threads. This multi-functionality allows a single unified mechanism to handle both levels of control, reducing overall device complexity compared to having separate independent systems.
3Adaptability or versatility
If multiple performance state hint sources are combined, then the adaptability to different workloads is improved, but the information integration complexity increases
Solution Approach 1:
The patent adds a thread-level dimension to the traditional package-level performance state control, creating a hierarchical two-dimensional hint system. This dimensional approach enables the system to adapt to different workloads at multiple granularities without requiring complex integration logic, as the hints naturally organize into layers with clear override relationships.
Solution Approach 2:
The patent implements preliminary action by having the system determine in advance whether thread-level or package-level hints should be used based on validity indicators. This pre-determination simplifies the integration process by establishing clear rules before information conflicts arise, reducing the complexity of real-time information integration while maintaining high adaptability to different workload scenarios.
Data Source
AI summary
In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.