Processor Power Controller Reactive Throttling
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Solution Overview
Problem
The increasing power requirements and energy consumption of computing systems, driven by advances in semiconductor processing and logic design, necessitate more efficient energy management in integrated circuits to reduce overall electricity usage, particularly in devices like servers, desktops, and mobile phones.
Innovation Solution
A processor with a power controller that uses reactive techniques for precision throttling of circuitry, isolating and penalizing high-current IP circuits while maintaining performance in constrained environments, ensuring current and power isolation between partitions, and avoiding cross-partition throttling or frequency loss, thereby optimizing energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If reactive power control with precision throttling is implemented, then energy consumption is reduced and performance under physical constraints is improved, but device complexity increases due to the need for global awareness and local control mechanisms
Solution Approach 1:
The processor is divided into multiple partitions with separate power domains, each having independent power control mechanisms. This segmentation allows localized power management without affecting other partitions, enabling precision throttling of specific high-current IP circuits while maintaining performance in constrained environments.
Solution Approach 2:
The system implements global awareness through monitoring power consumption across all partitions and provides feedback to local control mechanisms. This feedback loop enables reactive power control that dynamically adjusts throttling based on real-time power conditions, optimizing energy consumption while maintaining performance.
2Productivity
If isolation between partitions is implemented to prevent cross-partition throttling, then performance in constrained environments is maintained for well-behaved IP circuits, but device complexity increases due to partitioning and isolation mechanisms
Solution Approach 1:
The processor is divided into multiple partitions with separate power domains, each having independent power control mechanisms. This segmentation allows localized power management without affecting other partitions, enabling precision throttling of specific high-current IP circuits while maintaining performance in constrained environments.
Solution Approach 2:
Each partition is granted a specific power budget and has local control mechanisms that operate independently. Well-behaved IP circuits in one partition are not affected by power management actions in other partitions, allowing local optimization without global interference.
3Use of energy by moving object
If aggressive power management is applied to reduce energy consumption, then use of energy is reduced, but performance may be impacted due to throttling
Solution Approach 1:
The system applies power management selectively rather than uniformly across the entire processor. Only partitions or IP circuits exceeding their power budgets are throttled, while well-behaved circuits continue operating at full performance. This partial action approach reduces energy consumption without unnecessarily impacting overall performance.
Solution Approach 2:
The system dynamically changes operational parameters such as frequency and voltage for specific partitions or IP circuits based on their power consumption patterns. This allows aggressive power management for high-current circuits while maintaining optimal performance parameters for energy-efficient circuits.
Data Source
AI summary
In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.