Processor Power Management During Core Activation

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Solution Overview

Problem

Multi-core processors face inefficiencies due to power surges when activating hibernating processor cores, leading to increased short-term power requirements and difficulties in correcting peak power draw issues post-production.

Innovation Solution

A computing device with a power management system that adjusts operating limits of active processor cores based on the number of hibernating cores to be activated, ensuring power consumption remains within the limits of the power source, thereby reducing the likelihood of power surges during activation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the power source is oversized to accommodate peak power demands during processor core activation, then the power source can handle activation spikes, but this results in inefficiencies and increased cost

Engineering Contradiction:
Improvepower source capacityVSAvoidpower efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements dynamic adjustment of operating limits for processor cores based on real-time power availability and activation state. The system continuously monitors power conditions and adjusts operational parameters accordingly, transitioning from static to dynamic power management to optimize both reliability and efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (operating limits) of processor cores dynamically based on power conditions. By adjusting these parameters in response to activation events and power availability, the system avoids the need for oversized power sources while maintaining adequate power supply during critical transitions

Inventive Principle:
Principle #35Parameter changes

2Power

If additional hibernating processor cores are activated to increase processing power, then processing capability improves, but this causes a spike in power draw from the local power source

Engineering Contradiction:
Improveprocessing powerVSAvoidpower draw
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary actions by adjusting operating limits of active processor cores before hibernating cores are fully activated. This preparatory adjustment of power distribution prevents sudden power spikes during activation transitions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables rapid activation of hibernating processor cores by streamlining the power management process. Through pre-adjustment of operating limits and efficient power allocation, the system rushes through the activation process quickly, minimizing the duration and magnitude of power draw spikes

Inventive Principle:
Principle #21Skipping (Rushing through)

3Loss of energy

If the operating limit of active processor cores is adjusted based on the number of hibernating cores to be activated, then power consumption is managed within limits, but this requires complex power management control

Engineering Contradiction:
Improvepower consumption controlVSAvoidpower management system
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The power management system implements feedback mechanisms by monitoring the number of active and hibernating processor cores and automatically adjusting operating limits accordingly. This closed-loop control enables effective power consumption management through rule-based decisions rather than complex algorithms

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10261572B2Technologies for managing power during an activation cycle
Publication Date: 2019.04.16 INTEL CORP
  • US10261572B2 patent drawing
  • US10261572B2 patent drawing
  • US10261572B2 patent drawing

AI summary

Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.