Processor Power Domain Segmentation for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power saving techniques in processor devices, such as clock gating and power collapsing, either erase state information or require complex systems to preserve it, leading to unacceptable latency or increased power consumption, and there is a need for improved methods to minimize leakage current while maintaining state information.
Innovation Solution
A circuit architecture that separates power connections for processing logic and state information circuits, allowing for independent power collapsing, where an applications processor controls switches to keep state information circuits powered during idle states and reduce voltage to a retention level, while powering down logic circuits to minimize leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power collapsing is used to reduce leakage power, then power consumption is reduced, but state information is erased
Solution Approach 1:
The processing core is segmented into two distinct power domains: logic processing circuits and state information circuits. Each domain has separate power connections controlled by different switches, allowing independent power management. This segmentation enables selective power collapsing of logic circuits while maintaining power to state circuits, thus reducing leakage power without erasing state information.
Solution Approach 2:
Different power management strategies are applied to different parts of the system. The logic processing circuits receive full power during active operations, while state information circuits receive reduced retention voltage during idle states. This local differentiation of power quality allows optimal power savings without compromising state preservation.
2Loss of time
If state information is preserved during power down, then latency is reduced, but power consumption increases
Solution Approach 1:
The power management system dynamically adjusts voltage levels based on operational state. During active processing, logic circuits receive full operating voltage. During idle states, logic circuits are powered down while state circuits receive reduced retention voltage. This dynamic voltage adjustment minimizes power consumption while preserving state information to reduce latency upon revival.
Solution Approach 2:
The system periodically transitions between active and idle states, with the applications processor monitoring processing needs and controlling switch states accordingly. During idle periods, power is reduced to retention level; during active periods, full power is restored. This periodic power management reduces average power consumption while maintaining state information to enable quick resumption.
3Loss of energy
If separate power connections are used for logic and state circuits, then leakage power is minimized, but device complexity increases
Solution Approach 1:
The power distribution network is segmented into separate controllable domains with distinct switches for logic and state circuits. This segmentation enables independent control of power flow to each domain, allowing the system to minimize leakage current by selectively powering down logic circuits while maintaining state circuits, without significantly increasing overall device complexity.
Data Source
AI summary
Methods, systems, and circuits for preserving state information during power saving operations are disclosed. One example embodiment includes a circuit having a processing core, where the processing core includes logic processing circuits as well as circuits (e.g., flip-flops registers) that are used to store state information in the processing core. The logic processing circuits have power connections to a power rail that are subject to a switch, which can disconnect the power connections from the power rail. The circuits that are used to store state information have different power connections that are subject to a different switch. Therefore, the logic processing circuits and the state information circuits can be separately power-collapsed.