Processor Power Management via Dynamic Voltage Frequency Scaling
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Solution Overview
Problem
Existing processor management systems face significant latency issues during transitions between high and low power modes, particularly when switching due to unpredictable external stimuli, which can impact application performance and reaction times.
Innovation Solution
A method for dynamically managing processor power consumption using Dynamic Voltage/Frequency Scaling (DVFS) that allows optional switching between modes based on computational load, maximum latency, and application parameters, ensuring nominal operation without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the processor switches from high power mode to low power mode, then power consumption is reduced, but latency increases during mode transition
Solution Approach 1:
The patent applies preliminary action by predicting future computational loads and pre-positioning the processor in appropriate power modes before actual transitions are needed. The decision function uses historical data and predictive algorithms to anticipate when high or low power modes will be required, allowing the system to prepare for mode transitions in advance rather than reacting after latency has already occurred.
Solution Approach 2:
The patent implements dynamics by making the power mode selection adaptive and flexible rather than fixed. The decision function continuously monitors computational load patterns, external stimuli, and system state to dynamically adjust power modes in real-time. This allows the system to optimize between power savings and transition latency based on actual operating conditions rather than following a rigid schedule.
2Device complexity
If the processor uses empirical models for predicting computation time, then power management is simplified, but accuracy decreases when external stimuli trigger unexpected processing phases
Solution Approach 1:
The patent applies feedback by implementing a decision function that continuously monitors actual system behavior, external stimuli, and computational load patterns. The system uses feedback from these observations to refine its predictions and adjust power mode selections dynamically. This feedback mechanism allows the system to correct prediction errors and adapt to changing conditions without requiring overly complex empirical models.
Solution Approach 2:
The patent implements parameter changes by adjusting the decision function's input parameters and weighting factors based on observed system behavior. Rather than using fixed empirical models, the system dynamically modifies prediction parameters based on actual computational load patterns, external stimulus frequency, and transition latency measurements, improving accuracy without increasing model complexity.
3Speed
If the processor maintains high power mode continuously, then reaction time to external stimuli is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by maintaining high power mode only partially - specifically during periods when external stimuli are detected or predicted to occur. The decision function analyzes stimulus patterns and maintains appropriate power levels only when needed, rather than continuously. This partial activation approach reduces overall power consumption while ensuring fast response to actual stimuli when they occur.
Data Source
AI summary
A method for managing the power consumed in a processor executing an application, the application including several processing phases, each of which is associated with a computational load. The method includes defining a first nominal mode of consumption, defining at least one second mode of low consumption, and formulating a decision function making it possible optionally to switch from the nominal mode of consumption to the mode of low consumption during the transition from one processing phase to another processing phase of the application.