Processor Power Management Circuit for Performance Level Notifications

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Solution Overview

Problem

Existing processor technologies lack efficient mechanisms for dynamically managing and notifying the operating system of changes in processor performance levels, particularly in over-clocking scenarios, leading to suboptimal thread scheduling and resource allocation.

Innovation Solution

Implementing a power management circuit with a finite state machine that autonomously adjusts processor performance levels and generates interrupts to notify the operating system of changes, using status, interrupt, and capabilities registers to manage and control processor performance levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If processor performance levels are dynamically adjusted without hardware control mechanisms, then flexibility in performance management is improved, but system reliability and timely notification of performance changes deteriorate

Engineering Contradiction:

Improveflexibility in performance managementVSAvoidtimely notification of performance changes

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the finite state machine monitors processor performance levels and generates interrupts to notify the operating system of changes. This closed-loop feedback ensures that performance changes are reliably communicated to the OS, resolving the contradiction between flexibility and timely notification.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The finite state machine autonomously manages performance level adjustments and self-generates notifications to the operating system without requiring external software intervention. This self-service capability ensures reliable performance change notification while maintaining hardware-level control flexibility.

Inventive Principle:

Principle #25Self-service

2Ease of manufacture

If software-based performance management is used, then ease of implementation is improved, but system complexity and inefficiency in performance control increase

Engineering Contradiction:

Improveease of implementationVSAvoidsystem complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent replaces software-based performance management with a hardware-based finite state machine that directly controls processor performance levels. This substitution eliminates the need for complex software routines while providing more efficient and direct performance control, reducing overall system complexity despite adding hardware components.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The finite state machine acts as an intermediary hardware component between the processor and the operating system, simplifying the control mechanism by providing a dedicated hardware layer that manages performance transitions and generates standardized interrupts, thereby reducing system complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If hardware control mechanisms are implemented, then productivity and efficiency in performance management are improved, but device complexity increases

Engineering Contradiction:

Improveefficiency in performance managementVSAvoiddevice complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the performance management function into a dedicated finite state machine component that handles only performance level transitions and notifications. This segmentation isolates the complexity into a manageable hardware module, improving productivity by providing efficient performance control while containing device complexity within a specific component.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The finite state machine is designed to handle multiple performance management tasks including monitoring performance levels, determining transitions, adjusting processor frequency, and generating interrupts. This multi-functionality consolidates several operations into a single hardware component, improving productivity while minimizing the increase in overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12547564B2Apparatuses, methods, and systems for hardware control of processor performance levels

Publication Date: 2026.02.10 INTEL CORP

AI summary

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.