Processor Power Management Logic Latency Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computing systems do not utilize all available time in a low power state, leading to potential power savings being unrealized, as they typically return to a full power state upon receiving a break event without deferring non-critical events.
Innovation Solution
Implementing a power management logic that defers exit from a reduced power state based on negotiated platform latency tolerance, blocking non-critical break events during this period to extend the time spent in the low power state, thereby reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the system returns to full power state immediately upon receiving a break event, then responsiveness to events is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the power state transition timing based on event criticality. Non-critical break events are deferred to allow the system to remain in reduced power state longer, while critical events still trigger immediate transitions. This dynamic classification and differential handling resolves the contradiction by making responsiveness adaptive rather than static.
Solution Approach 2:
The system changes the timing parameter of power state transitions based on event characteristics. By modifying when the transition occurs (immediate vs. deferred), the system optimizes between responsiveness and power consumption. The break event handling parameter is adjusted according to event priority, allowing the system to stay in low power state longer for non-critical events.
2Use of energy by moving object
If the system defers exit from reduced power state for non-critical events, then power consumption decreases, but event handling latency increases
Solution Approach 1:
The system applies different quality of service to different event types. Critical events receive immediate attention with zero deferred latency, while non-critical events are eligible for deferral. This local differentiation allows the system to reduce overall power consumption without significantly impacting critical event handling, as only a subset of events experiences deferred processing.
Solution Approach 2:
The break event queue autonomously manages event timing without external intervention. The queue automatically defers non-critical events and allows critical events to proceed immediately, making the system self-regulating. This self-service mechanism resolves the contradiction by internally balancing power savings against latency requirements based on event priority.
3Duration of action of stationary object
If the system blocks non-critical break events during reduced power state, then time in low power state increases, but event processing is delayed
Solution Approach 1:
The system changes the processing timing parameter for different event priorities. Non-critical events are blocked with deferred processing, extending the reduced power state duration. The blocking parameter is selectively applied based on event criticality, allowing the system to maximize low power state occupancy while ensuring critical events remain unaffected.
Solution Approach 2:
The system applies partial blocking - only non-critical events are blocked during reduced power state, while critical events are allowed to proceed immediately. This partial action approach achieves power savings without excessive delay, as only a portion of events (non-critical ones) experience the blocking effect.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.