Real-Time Processor Power Meter for Proportional Throttling
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Solution Overview
Problem
Current power management systems in processors assume a worst-case virus condition to manage power, leading to unnecessary performance penalties by throttling operating frequencies, even for minor power excursions, which can result in inefficient use of resources and increased costs for power supply designs.
Innovation Solution
Implementing a proportional throttling scheme that measures the dynamic capacitance of applications and adjusts processor power consumption accordingly, using a new GPIO path to initiate throttling based on real-time power inference, allowing for more precise control over power usage and performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor assumes a worst-case virus condition and applies maximum throttling to stay within power limits, then power management reliability is improved, but processor performance suffers unnecessary penalties
Solution Approach 1:
The patent changes the throttling parameter from a fixed maximum reduction to a variable proportional reduction. The power management module now applies throttling proportional to the measured power excursion magnitude, where minor excursions result in minimal throttling and major excursions result in maximum throttling. This resolves the contradiction by maintaining reliability through appropriate throttling while preserving performance when power excursions are minor.
Solution Approach 2:
The patent introduces dynamic adaptability to the throttling mechanism. Instead of a static worst-case assumption, the system dynamically adjusts throttling based on real-time power measurements. The power management module continuously monitors power consumption and applies proportional throttling that adapts to the actual power excursion, resolving the contradiction between reliability and performance.
2Use of energy by stationary object
If the processor throttles operating frequency for minor power excursions to ensure power limit compliance, then power consumption is controlled, but performance is unnecessarily reduced
Solution Approach 1:
The patent changes the throttling parameter from a fixed maximum reduction to a variable proportional reduction. The power management module now applies throttling proportional to the measured power excursion magnitude, where minor excursions result in minimal throttling and major excursions result in maximum throttling. This resolves the contradiction by maintaining reliability through appropriate throttling while preserving performance when power excursions are minor.
Solution Approach 2:
The patent applies partial throttling action proportional to the power excursion rather than always applying full maximum throttling. For minor power excursions, only a small proportional throttling is applied, which is sufficient to maintain power compliance without excessive performance impact. This resolves the contradiction by using just enough throttling action to control power consumption while minimizing performance loss.
3Reliability
If the system uses a fixed power threshold approach with maximum throttling, then power limit compliance is ensured, but power supply design capacity requirements increase
Solution Approach 1:
The patent changes the throttling parameter from a fixed maximum reduction to a variable proportional reduction. The power management module now applies throttling proportional to the measured power excursion magnitude, where minor excursions result in minimal throttling and major excursions result in maximum throttling. This resolves the contradiction by maintaining reliability through appropriate throttling while preserving performance when power excursions are minor.
Data Source
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AI summary
A scheme is provided for a processor to measure or estimate the dynamic capacitance (Cdyn) associated with an executing application and take a proportional throttling action. Proportional throttling has significantly less impact on performance and hence presents an opportunity to get back the lost bins and proportionally clip power if it exceeds a specification threshold. The ability to infer a magnitude of power excursion of a power virus event (and hence, the real Cdyn) above a set power threshold limit enables the processor to proportionally adjust the processor operating frequency to bring it back under the limit. With this scheme, the processor distinguishes a small power excursion versus a large one and reacts proportionally, yielding better performance.