Processor Power Mode Management via PMIC Validation
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Solution Overview
Problem
Existing processor power mode management systems face challenges in ensuring robust and secure transitions between normal and low power modes, particularly in safety-critical applications, where miscommunication between the processor and Power Management IC can lead to unexpected power downs, posing safety risks.
Innovation Solution
A system and method that utilizes a Power Management IC (PMIC) with dedicated modules for power management and safety processing, including a power management processing module and a safety processing module, to ensure accurate and safe transitions between power modes by using a two-step standby process, CRC logic for communication integrity, and watchdog timers to prevent prolonged low power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a processor uses a low power mode to minimize power consumption during inactivity, then power consumption is reduced, but the risk of unexpected power downs and safety failures increases due to potential miscommunication with the PMIC
Solution Approach 1:
The patent implements a two-step standby entry process where the processor first sends a digital code to the PMIC, then waits for acknowledgment before actually entering standby mode. This preliminary validation sequence ensures communication integrity before power reduction, preventing unexpected power downs while allowing the processor to safely enter low power mode.
Solution Approach 2:
The PMIC provides feedback to the processor through acknowledgment signals and status indicators during the standby transition process. This feedback mechanism allows the processor to verify successful communication and proper state transitions, ensuring safety-critical functions are maintained even during power mode changes.
2Use of energy by moving object
If the processor transitions to low power mode without robust validation, then power consumption is reduced, but communication errors and unexpected power downs occur
Solution Approach 1:
Before transitioning to standby mode, the processor performs preliminary actions including sending a validation digital code to the PMIC and receiving acknowledgment. This pre-validation sequence ensures communication accuracy is maintained, preventing data loss or miscommunication during the power mode transition.
Solution Approach 2:
The system implements preliminary anti-action by using CRC logic and validation codes to prevent communication errors before they can occur. The digital code exchange and acknowledgment mechanism proactively counteracts potential communication failures, ensuring data integrity during standby transitions.
3Reliability
If the system implements robust validation and two-step processes for standby transitions, then safety and reliability are improved, but device complexity increases
Solution Approach 1:
The patent segments the standby entry process into distinct steps: sending digital code, receiving acknowledgment, validating communication, and then transitioning to standby mode. This segmentation of complex control logic into manageable stages improves reliability while making the complexity more tractable and verifiable.
Solution Approach 2:
The PMIC acts as an intermediary between the processor and the power management functions. It handles the complex validation logic, CRC checking, and state machine management, offloading complexity from the processor while ensuring safe and reliable power mode transitions.
4Use of energy by moving object
If the processor enters standby mode without timeout protection, then power consumption is reduced, but the system may remain in low power state too long causing safety issues
Solution Approach 1:
The patent implements periodic watchdog timers that monitor the processor's activity during and after standby mode. These timers provide periodic checks to ensure the processor transitions back to active mode within expected timeframes, preventing the system from remaining in low power state indefinitely while still allowing legitimate extended standby periods.
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AI summary
A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.