Processor Power Controller External Override Mechanism
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Solution Overview
Problem
The increasing power requirements and energy consumption of multicore processors pose a significant challenge for energy efficiency, particularly in computing systems where existing power management techniques are limited in their ability to dynamically adjust performance states based on workload and external factors.
Innovation Solution
The implementation of a power controller that autonomously selects performance states using OS and thread-supplied hints, with the option to override these hints based on processor-external override information via the Platform Environment Control Interface (PECI), allowing for dynamic voltage and frequency scaling and independent voltage regulation for each core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If autonomous hardware power control is implemented, then energy efficiency is improved, but adaptability to external conditions deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the hardware performance state controller receives override information from external entities (such as management controllers or operating systems) and adjusts its autonomous control accordingly. This allows the system to maintain energy efficiency while adapting to external conditions through continuous feedback loops that modify performance state selections based on external inputs.
Solution Approach 2:
The patent introduces dynamic control by allowing the hardware performance state controller to transition between autonomous operation and external override modes. The system can dynamically adjust its control behavior based on configured priorities and override information, enabling flexible adaptation to varying operational requirements while maintaining core autonomous power management capabilities.
2Productivity
If dynamic performance state adjustment is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the hardware performance state controller to autonomously select and manage performance states without requiring constant external intervention. The controller automatically adjusts processor performance based on workload conditions and can independently handle power management tasks, thereby improving productivity while minimizing the complexity burden from external control mechanisms.
Solution Approach 2:
The patent segments the power management function by separating autonomous hardware control from external software control. The hardware performance state controller operates as an independent entity that can make decisions based on internal conditions, while external entities provide override information only when necessary. This segmentation reduces the complexity of coordinated control by clearly defining boundaries between autonomous and external control domains.
3Adaptability or versatility
If external override capability is added, then adaptability to external conditions is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary interface (such as PECI - Platform Environment Control Interface) that mediates between external entities and the hardware performance state controller. This standardized intermediary layer simplifies the complexity by providing a uniform interface for receiving override information, abstracting the communication details from the core control logic and enabling external condition adaptability without proportionally increasing internal system complexity.
Data Source
AI summary
In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.