Multi-Die Processor Power Allocation Without Sorting Latency
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Solution Overview
Problem
Existing power distribution methods in processors with multiple CPU core dies lead to increased circuit complexity and latency when the number of dies increases, particularly due to the need for strict equal power allocation, which is not addressed by existing token-based distribution techniques.
Innovation Solution
A processor design that includes a first allowable power determination circuit for the entire system and a second determination circuit for individual dies, along with a transmission circuit to manage power distribution efficiently, ensuring the circuit complexity does not increase disproportionately with the number of CPU core dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If strict equal power allocation is performed to correspond to request power of each CPU core die, then power distribution accuracy is improved, but circuit complexity increases
Solution Approach 1:
The power allocation circuit is divided into two independent determination circuits: a first determination circuit that operates at the system level to determine total allowable power, and a second determination circuit that operates at the die level to allocate power to individual CPU core dies. This segmentation allows each circuit to handle a specific portion of the power allocation task, reducing the complexity burden on any single circuit while maintaining accurate power distribution.
2Productivity
If the number of CPU core dies is doubled, then processing capability is improved, but circuit scale increases
Solution Approach 1:
The power allocation circuit is designed with a universal structure that can handle any number of CPU core dies through the hierarchical determination process. The first determination circuit calculates total allowable power for the entire system, and the second determination circuit distributes this power proportionally to individual dies based on their request power. This universal design allows the same circuit architecture to scale efficiently as the number of dies increases, without requiring a complete redesign for each additional die.
3Measurement precision
If sort circuit for request power is added, then power allocation accuracy is improved, but latency increases
Solution Approach 1:
Instead of implementing a complete sort circuit that would order all request powers to achieve optimal allocation, the invention uses a partial action approach where the second determination circuit calculates power allocation based on the relationship between request power and the total allowable power. The allocation ratio is determined by dividing the total allowable power by the sum of all request powers, and then multiplying this ratio by each individual request power. This partial calculation approach achieves sufficient power allocation accuracy without the latency penalty of full sorting operations.
Data Source
AI summary
In a processor, a first allowable power determination circuit determines a smaller value of first request power requested by an entire plurality of calculation devices or first power limit for the entire plurality of calculation devices as a first allowable power allowable to the entire plurality of calculation devices, a second allowable power determination circuit that determines second allowable power for each calculation device based on a smaller value of second request power or second power limit for each calculation device and the first allowable power, and a transmission circuit that transmits the second allowable power to the calculation device to cause the calculation device to receive supply of the second allowable power.